Cypress PSoC CY8CTMG20 Series, Technical Reference Manual

Page: 113 / 308

PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C 113
Digital Clocks
14.2.2 OUT_P0 Register
This register enables specific internal signals to be output to
Port 0 pins. The GPIO drive modes must be specified to
support the desired output mode (registers PRT0DM1 and
PRT0DM0). If a pin is enabled for output by a bit in this reg-
ister, the corresponding signal has priority over any other
internal function that may be configured to output to that pin.
Bit 7: P0P7D. ‘0‘ selects main system clock (SYSCLK).
‘1‘ selects TrueTouch signal depending on PRS_CR and
CS_CR0 register settings.
Bit 6: P0P7EN. This bit enables pin P0[7] for output of the
signal selected by P0P7D. ‘0 ‘is no internal signal output to
P0[7]. ‘1‘ outputs the signal selected by P0P7D onto P0[7].
Bit 5: P0P4D.
‘0‘ selects Timer Output (TIMEROUT). ‘1‘
selects CLK32.
Note : During sleep mode these outputs will not be passed
through to P0[4].
Bit 4: P0P4EN. This bit enables pin P0[4] for output of the
signal selected by P0P4D. ‘0‘ is no internal signal output to
P0[4]. ‘1‘ outputs the signal selected by P0P4D onto P0[4].
14.2.3 OUT_P1 Register
The Output Override to Port 1 Register (OUT_P1) enables
specific internal signals to output to Port 1 pins. If any other
function, such as I2C, is enabled for output on these pins,
that function has higher priority than the OUT_P1 signals.
Bit 7: P16D. Bit selects the data output to P1[6] when
P16EN is high. In CY8CTMG20x and CY8CTST200 Timer
Output and CLK32 are available on P0[4] as well, but out-
puts on P0[4] will not be passed through during sleep
modes. Please refer to the OUT_P0 register for more
details.
0 - Select Timer output (TIMEROUT)
1 - Select CLK32
Bit 6: P16EN.
This bit enables pin P1[6] for signal output
selected by the P16D bit.
0 - No internal signal output to P1[6]
1 - Output the signal selected by P16D to P1[6]
Bit 5: P14D. This bit selects the data output to P1[4] when
P14EN is high and 14DB is low.
Bit 4: P14EN.
This bit enables pin P1[4] for output of the
signal selected by the P14D bit.
Bit 3: P12D. This bit selects data output to P1[2] when
P12EN is high. TrueTouch signals are available on P0[7] as
well. Please refer OUT_P0 register for more details.
Bit 2: P12EN. This bit enables pin P1[2] for output of the
signal selected by the P12D bit.
Bit 1: P10D. This bit selects data output to P1[0] when
P10EN is high.
Bit 0: P10EN. Bit enables pin P1[0] for output of the signal
selected by the P10D bit.
0 - No internal signal output to P1[0]
1 - Output the signal selected by P10D to P1[0]
For additional information, refer to the OUT_P1 register on
page 273 .
14.2.4 OSC_CR0 Register
The Oscillator Control Register 0 (OSC_CR0) configures
various features of internal clock sources and clock nets. Bit 7: X32ON. This bit enables the 32 kHz external crystal
oscillator (ECO) when set high. See the Application Over-
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access
1,D1h OUT_P0 P0P7D P0P7EN P0P4D P0P4EN RW : 00
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access
1,DDh OUT_P1 P16D P16EN P14D P14EN P12D P12EN P10D P10EN RW : 00
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access
1,E0h OSC_CR0 X32ON Disable Buzz No Buzz Sleep[1:0] CPU Speed[2:0] RW : 01
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