Cypress PSoC CY8CTMG20 Series, Technical Reference Manual

Page: 187 / 308

PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C 187
21. Register Reference
This chapter is a reference for all the PSoC device registers in address order, for Bank 0 and Bank 1. The most detailed
descriptions of the PSoC registers are in the Register Definitions section of each chapter. The registers that are in both banks
are incorporated with the Bank 0 registers, designated with an ‘x’, rather than a ‘0’ preceding the comma in the address. Bank
0 registers are listed first and begin on page
188 . Bank 1 registers are listed second and begin on page 259 . A condensed
view of all the registers is shown in the register mapping tables starting on page 183 .
21.1 Maneuvering Around the Registers
For ease-of-use, this chapter has been formatted so that there is one register per page, although some registers use two
pages. On each page, from top to bottom, there are four sections:
1. Register name and address (from lowest to highest).
2. Register table showing the bit organization, with reserved bits grayed out.
3. Written description of register specifics or links to additional register information.
4. Detailed register bit descriptions.
Use the register tables, in addition to the detailed register bit descriptions, to determine which bits are reserved. Reserved bits
are grayed table cells and are not described in the bit description section. Reserved bits must always be written with a value
of ‘0’. For all registers, an ‘x’ before the comma in the address field indicates that the register can be accessed or written to no
matter what bank is used. For example, the M8C flag register’s (CPU_F) address is ’x,F7h’ meaning it is located in bank 0
and bank 1 at F7h.
21.2 Register Conventions
The following table lists the register conventions that are specific to this chapter.
Register Conventions
Convention Example Description
‘x’ in a register name PRTxIE Multiple instances/address ranges of the same register.
R R : 00 Read register or bit(s).
W W : 00 Write register or bit(s).
O RO : 00 Only a read/write register or bit(s).
L RL : 00 Logical register or bit(s).
C RC : 00 Clearable register or bit(s).
00 RW : 00 Reset value is 0x00 or 00h.
XX RW : XX Register is not reset.
0, 0,04h Register is in bank 0.
1, 1,23h Register is in bank 1.
x, x,F7h Register exists in register bank 0 and register bank 1.
Empty, grayed-out table cell Reserved bit or group of bits, unless otherwise stated.
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