Cypress PSoC CY8CTMG20 Series, Technical Reference Manual

Page: 188 / 308

188 PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
PRTxDR
0,00h
21.3 Bank 0 Registers
The following registers are all in bank 0 and are listed in address order. An ‘x’ before the comma in the register’s address indi-
cates that the register can be accessed in Bank 0 and Bank 1, independent of the XIO bit in the CPU_F register. Registers
that are in both Bank 0 and Bank 1 are listed in address order in Bank 0. For example, the RDIxLT1 register has an address
of x,B4h and is listed only in Bank 0 but is accessed in both Bank 0 and Bank 1.
21.3.1 PRTxDR
Port Data Registers
These registers allow for write or read access, or the current logical equivalent, of pin voltage.
The upper nibble of the PRT4DR register returns the last data bus value when read. You need to mask it off before using this
information. For additional information, refer to the
Register Definitions on page 59 in the GPIO chapter.
7:0 Data[7:0] Write value to port or read value from port. Reads return the state of the pin, not the value in the
PRTxDR register.
Individual Register Names and Addresses: 0,00h
PRT0DR : 0,00h PRT1DR : 0,04h PRT2DR : 0,08h PRT3DR : 0,0Ch
PRT4DR : 0,10h
7 6 5 4 3 2 1 0
Access : POR RW : 00
Bit Name Data[7:0]
Bit Name Description
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