PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
259
PRTxDM0
1,00h
21.4
Bank 1 Registers
The following registers are all in bank 1 and are listed in address order. Registers that are in both Bank 0 and Bank 1 are
listed in address order in the section titled
21.4.1
PRTxDM0
Port Drive Mode Bit Registers 0
This register is one of two registers where the combined value determines the unique drive mode of each bit in a GPIO port.
In register PRTxDM0 there are four possible drive modes for each port pin. Two mode bits are required to select one of these
modes, and these two bits are spread into two different registers (PRTxDM0 and
). The bit position of
the effected port pin (for example, Pin[2] in Port 0) is the same as the bit position of each of the two Drive Mode register bits
that control the drive mode for that pin (for example, bit[2] in PRT0DM0 and bit[2] in PRT0DM1). The two bits from the two
registers are treated as a group. These are referred to as DM1 and DM0, or together as DM[1:0].
All drive mode bits are shown in the sub-table below ([1
0
] refers to the combination (in order) of bits in a given bit position);
however, this register only controls the
of the drive mode.
The upper nibble of the PRT4DM0 register returns the last data bus value when read. You need to mask it off prior to using
this information. For additional information, refer to the
Register Definitions on page 59
in the GPIO chapter.
7:0
Drive Mode 0[7:0]
Bit 0 of the drive mode, for each of 8-port pins, for a GPIO port.
[
1
0]
Pin Output High
Pin Output Low
Notes
0
0
b
Resistive
Strong
0
1
b
Strong
Strong
1
0
b
High Z
High Z
Reset state. Digital input disabled for zero power.
1
1
b
High Z
Strong
I2C compatible mode. For digital inputs, use this
mode with data bit (PRTxDR register) set high.
Note
A bold digit in the table above signifies that the digit is used in this register.
Individual Register Names and Addresses:
1,00h
PRT0DM0 : 1,00h
PRT1DM0 : 1,04h
PRT2DM0 : 1,08h
PRT3DM0 : 1,0Ch
PRT4DM0 : 1,10h
7
6
5
4
3
2
1
0
Access : POR
RW : 00
Bit Name
Drive Mode 0[7:0]
Bit
Name
Description
Summary of Contents for PSoC CY8CTMG20 Series
Page 4: ...4 Contents Overview Feedback...
Page 26: ...26 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C Section B PSoC Core Feedback...
Page 82: ...82 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C Sleep and Watchdog Feedback...
Page 134: ...134 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C I2C Slave Feedback...
Page 142: ...142 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C System Resets Feedback...
Page 160: ...160 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C SPI Feedback...
Page 182: ...182 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C Full Speed USB Feedback...
Page 302: ...302 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C Glossary Feedback...
