260
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
PRTxDM1
1,01h
21.4.2
PRTxDM1
Port Drive Mode Bit Registers 1
This register is one of three registers where the combined value determines the unique drive mode of each bit in a GPIO port.
In register PRTxDM1 there are four possible drive modes for each port pin. Two mode bits are required to select one of these
modes, and these two bits are spread into two different registers (PRTxDM1 and
). The bit position of
the effected port pin (for example, Pin[2] in Port 0) is the same as the bit position of each of the two Drive Mode register bits
that control the drive mode for that pin (for example, bit[2] in PRT0DM0 and bit[2] in PRT0DM1). The two bits from the two
registers are treated as a group. These are referred to as DM1 and DM0, or together as DM[1:0].
All drive mode bits are shown in the sub-table below ([
1
0] refers to the combination (in order) of bits in a given bit position);
however, this register only controls the most significant bit (MSb) of the drive mode.
The upper nibble of the PRT4DM1 register returns the last data bus value when read. You need to mask it off before using
this information. For additional information, refer to the
Register Definitions on page 59
in the GPIO chapter.
7:0
Drive Mode 1[7:0]
Bit 1 of the drive mode, for each of 8-port pins, for a GPIO port.
[1
0
]
Pin Output High
Pin Output Low
Notes
0
0b
Resistive
Strong
0
1b
Strong
Strong
1
0b
High Z
High Z
Reset state. Digital input disabled for zero power.
1
1b
High Z
Strong
I2C compatible mode. For digital inputs, use this
mode with data bit (PRTxDR register) set high.
Note
A bold digit in the table above signifies that the digit is used in this register.
Individual Register Names and Addresses:
1,01h
PRT0DM1 : 1,01h
PRT1DM1 : 1,05h
PRT2DM1 : 1,09h
PRT3DM1 : 1,0Dh
PRT4DM1 : 1,11h
7
6
5
4
3
2
1
0
Access : POR
RW : FF
Bit Name
Drive Mode 1[7:0]
Bit
Name
Description
Summary of Contents for PSoC CY8CTMG20 Series
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