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PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
Section A: Overview
Top Level Architecture
The PSoC block diagram on the next page illustrates the
top-level architecture of the CY8CTMG20x and
CY8CTST200 devices. Each major grouping in the diagram
is covered in this manual in its own section: PSoC Core,
TrueTouch System, and the System Resources. Banding
these three main areas together is the communication net-
work of the system
PSoC Core
The PSoC Core is a powerful engine that supports a rich
instruction set. It encompasses the
for data storage,
an
controller for easy program execution to new
addresses, sleep and watchdog timers, a regulated 3.0V
output option is provided for Port 1 I/Os, and multiple
sources that include the IMO (internal main oscillator) and
ILO (internal low speed oscillator) for precision, programma-
ble clocking.
The CPU core, called the M8C, is a powerful processor with
speeds up to 24 MHz. The M8C is a four MIPS 8-
vard architecture microprocessor. Within the CPU core are
the
and
memory components that provide
flexible programming.
PSoC GPIOs provide connection to the CPU and the True-
Touch resources of the device. Each pin’s drive mode is
selectable from four options, allowing great flexibility in
external interfacing. Every pin also has the capability to gen-
erate a system interrupt on low level and change from last
read.
TrueTouch™ System
The TrueTouch System is composed of comparators, refer-
ence drivers, I/O multiplexers, and digital logic to support
various capacitive sensing algorithms. Various reference
selections are provided. Digital logic is mainly comprised of
counters and timers.
System Resources
The System Resources provide additional PSoCcapability.
These system resources include:
■
Digital clocks to increase the flexibility of the PSoC pro-
grammable system-on-chip.
■
I2C functionality with "no bus stalling.”
■
Various system resets supported by the M8C.
■
Power-On-Reset (POR) circuit protection.
■
SPI master and slave functionality.
■
A programmable timer to provide periodic interrupts.
■
Clock boost network providing a stronger signal to
switches.
■
Full-speed USB interface for USB 2.0 communication
with 512 bytes of dedicated buffer memory and an inter-
nal 3V regulator.
Summary of Contents for PSoC CY8CTMG20 Series
Page 4: ...4 Contents Overview Feedback...
Page 26: ...26 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C Section B PSoC Core Feedback...
Page 82: ...82 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C Sleep and Watchdog Feedback...
Page 134: ...134 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C I2C Slave Feedback...
Page 142: ...142 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C System Resets Feedback...
Page 160: ...160 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C SPI Feedback...
Page 182: ...182 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C Full Speed USB Feedback...
Page 302: ...302 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C Glossary Feedback...
