Cypress PSoC CY8CTMG20 Series, Technical Reference Manual

Page: 103 / 308

PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C 103
Comparators
13.2 Register Definitions
The following registers areassociated with the Comparators in the CY8CTMG20x and CY8CTST200 PSoC devices and are
listed in address order. For a complete table of the comparator registers, refer to the
TrueTouch Register Summary on
page 84 . Each register description has an associated register table showing the bit structure for that register. Register bits
that are grayed out throughout this document are reserved bits and are not detailed in the register descriptions that follow.
Always write reserved bits with a value of ‘0’.
13.2.1 CMP_RDC Register
The Comparator Read/Clear Register (CMP_RDC) reads
the state of the comparator data signal and the latched
state of the comparator.
Bit 5: CMP1D. Comparator 1 Data State. This is a read
only bit and returns the dynamically changing state of the
comparator.
Bit 4: CMP0D. Comparator 0 Data State. This bit is a
read-only bit and returns the dynamically changing state
of the comparator.
Bit 1: CMP1L. Comparator 1 Latched State. This bit is
set and held high whenever the comparator 1 LUT goes
high since the last time this register was read. Refer to the
CRST1 bit in the CMP_CR1 register for information on
how the latch is cleared.
Bit 0: CMP0L. Comparator 0 Latched State. This bit is
set and held high whenever the comparator 0 LUT goes
high since the last time this register was read. Refer to the
CRST0 bit in the CMP_CR1 register for information on
how the latch is cleared.
For additional information, refer to the CMP_RDC register
on page 205 .
13.2.2 CMP_MUX Register
The Comparator Multiplexer Register (CMP_MUX) con-
tains control bits for input selection of comparators 0 and
1.
Bits 7 and 6: INP1[1:0]. These bits select the positive
input.
Bits 5 and 4: INN1[1:0]. These bits select the negative
input.
Bits 3 and 2: INP0[1:0]. These bits select the positive
input data source for comparator 0.
Bits 1 and 0: INN0[1:0].
These bits select the negative
input data source for comparator 0.
For additional information, refer to the CMP_MUX register
on page 206 .
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access
0,78h CMP_RDC CMP1D CMP0D CMP1L CMP0L # : 00
LEGEND
# Access is bit specific.
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access
0,79h CMP_MUX INP1[1:0] INN1[1:0] INP0[1:0] INN0[1:0] RW : 00
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