228
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
I2C_ADDR
0,CAh
21.3.40 I2C_ADDR
I
2
C Slave Address Register
This register holds the slave’s 7-bit address.
When hardware address compare mode is not enabled in the
register, this register is not in use. In the table
above, note that the reserved bit is a grayed table cell and not described in the bit description section below. Always write
reserved bits with a value of ‘0’. For additional information, refer to the
Register Definitions on page 122
in the I2C Slave
chapter.
6:0
Slave Address[6:0]
These seven bits hold the slave’s own device address.
Individual Register Names and Addresses:
0,CAh
0,D0h
I2C_ADDR : 0,CAh
7
6
5
4
3
2
1
0
Access : POR
RW : 00
Bit Name
Slave Address[6:0]
Bit
Name
Description
Summary of Contents for PSoC CY8CTMG20 Series
Page 4: ...4 Contents Overview Feedback...
Page 26: ...26 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C Section B PSoC Core Feedback...
Page 82: ...82 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C Sleep and Watchdog Feedback...
Page 134: ...134 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C I2C Slave Feedback...
Page 142: ...142 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C System Resets Feedback...
Page 160: ...160 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C SPI Feedback...
Page 182: ...182 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C Full Speed USB Feedback...
Page 302: ...302 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C Glossary Feedback...
