PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
4. RAM Paging
This chapter explains the PSoC device’s use of RAM Paging and its associated registers. For a complete table of the RAM
paging registers, refer to the
Summary Table of the Core Registers on page 24
. For a quick reference of all PSoC registers in
address order, refer to the
Register Reference chapter on page 187
.
4.1
Architectural Description
The M8C is an 8-bit CPU with an 8-bit memory address bus.
The memory address bus allows the M8C to access up to
256 bytes of SRAM, to increase the amount of available
SRAM and preserve the M8C
language. The
PSoC device has 1K and 2K bytes of SRAM with eight
pages of memory architecture.
To take full advantage of the paged memory architecture of
the PSoC device, you use several registers and manage
two CPU_F register bits. However, the Power On Reset
(POR) value for all of the paging registers and CPU_F bits is
zero. This places the PSoC device in a mode identical to
devices with only 256 bytes of SRAM. There is no need to
understand all of the Paging registers to take advantage of
the additional SRAM available in some devices. To use the
additional SRAM pages you modify the memory paging logic
reset state.
The memory paging architecture consists of five areas:
■
Stack Operations
■
Interrupts
■
MVI Instructions
■
Current Page Pointer
■
Indexed Memory Page Pointer
The first three of these areas do not depend upon the
CPU_F register's PgMode bits and are covered in the next
subsections after Basic Paging. The function of the last two
depend upon the CPU_F PgMode bits and are covered last.
4.1.1
Basic Paging
To increase the amount of SRAM, the M8C accesses mem-
ory page bits. The memory page bits are located in the
CUR_PP register and allow for selection of one of eight
SRAM pages. In addition to setting the page bits, Page
mode is enabled by setting the CPU_F[7] bit. If Page mode
is not enabled, the page bits are ignored and all non-stack
memory access is directed to Page 0.
After Page mode is enabled and the page bits are set, all
instructions that operate on memory access the SRAM page
indicated by the page bits. The exceptions to this are the
instructions that operate on the stack and the
MVI
instruc-
tions:
PUSH
,
POP
,
LCALL
,
RETI
,
RET
,
CALL
, and
MVI
. See
the description of
and
below for a more detailed discussion.
Figure 4-1. Data Memory Organization
Page 0
SRAM
256 Bytes
ISR
Page 6
SRAM
256 Bytes
Page 5
SRAM
256 Bytes
Page 3
SRAM
256 Bytes
Page 2
SRAM
256 Bytes
Page 1
SRAM
256 Bytes
Page 7
SRAM
256 Bytes
Page 4
SRAM
256 Bytes
00h
FFh
Summary of Contents for PSoC CY8CTMG20 Series
Page 4: ...4 Contents Overview Feedback...
Page 26: ...26 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C Section B PSoC Core Feedback...
Page 82: ...82 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C Sleep and Watchdog Feedback...
Page 134: ...134 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C I2C Slave Feedback...
Page 142: ...142 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C System Resets Feedback...
Page 160: ...160 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C SPI Feedback...
Page 182: ...182 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C Full Speed USB Feedback...
Page 302: ...302 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C Glossary Feedback...
