Cypress PSoC CY8CTMG20 Series Technical Reference Manual Download Page 118

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PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C

I2C Slave

The I

C block controls the data (SDA) and the clock (SCL)

to the external I

C interface through direct connections to

two dedicated GPIO pins. When I

C is enabled, these GPIO

pins are not available for general purpose use. The PSoC
CPU firmware interacts with the block through I/O register
reads and writes, and firmware synchronization is imple-
mented through polling and/or interrupts.

In the default operating mode, which is firmware compatible
with previous versions of I

C slave modules, the I

C bus is

stalled upon every received address or byte, and the CPU is
required to read the data or supply data as required before
the I

C bus continues. However, this I

C Slave Enhanced

module provides new data buffering capability as an
enhanced feature. In the EZI2C buffering mode, the I

slave interface appears as a 32-byte RAM buffer to the
external I

C master. Using a simple predefined protocol, the

master controls the read and write pointers into the RAM.
When this method is enabled, the slave never stalls the bus.
In this protocol, the data available in the RAM (this is man-
aged by the CPU) is valid.

15.1.1

Basic I

C Data Transfer

Figure 15-2

shows the basic form of data transfers on the

C bus with a 7-bit address format. For a more detailed

description, see the Philips Semiconductors (now NXP
Semiconductors) I

C-Bus Specification, version 2.1.

A Start condition (generated by the master) is followed by a
data byte, consisting of a 7-bit slave address (there is also a
10-bit address mode) and a read/write (RW) bit. The RW bit
sets the direction of data transfer. The addressed slave is
required to acknowledge (ACK) the bus by pulling the data
line low during the ninth bit time. If the ACK is received, the
transfer proceeds and the master transmits or receives an
indeterminate number of bytes, depending upon the RW
direction. If, for any reason, the slave does not respond with
an ACK, a Stop condition is generated by the master to ter-
minate the transfer or a Restart condition is generated for a
retry attempt.

Figure 15-2. Basic I

C Data Transfer with 7-Bit Address Format

15.2

Application Overview

There are two modes of slave operation, which are differen-
tiated by how the I

C block synchronizes CPU interaction,

how and when stalling of the I

C bus is done, and data buff-

ered.

15.2.1

Slave Operation

When Slave mode is enabled, it is continually listening on
the bus for a Start condition. When detected, the transmitted
address/RW byte is received and read from the I

C block by

firmware. At the point where eight bits of the address/RW
byte are received, a byte complete interrupt is generated.
On the following low of the clock, the bus is stalled by hold-
ing the SCL line low until the PSoC device has had a chance
to read the address byte and compare it to its own address.
It Issues an ACK or NACK command based upon that com-
parison.

If there is an address match, the RW bit determines how the
PSoC device sequences the data transfer in Slave mode, as
shown in the two branches of

Figure 15-3

. I

C handshaking

methodology (slave holds the SCL line low to “stall” the bus)
is used, as necessary, to give the PSoC device time to
respond to the events and conditions on the bus.

Figure 15-3

is a graphical representation of a typical data

transfer from the slave perspective.

START

7-Bit Address

R/W

ACK

8-Bit Data

ACK/NACK

STOP

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