Cypress PSoC CY8CTMG20 Series, Technical Reference Manual

Page: 231 / 308

PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C 231
CPU_BP
0,CDh
21.3.43 CPU_BP
CPU Base Address Pointer Register
This register contains the base address value of the RAM data buffer.
In the table above, note that reserved bits are grayed table cells and are not described in the bit description section below.
Always write reserved bits with a value of ‘0’. For additional information, refer to the
Register Definitions on page 122 in the
I2C Slave chapter.
4:0 CPU Base Pointer[4:0] This register value is completely controlled by I/O writes by the CPU. Firmware routines must set this
register. Similar to the I2C_BP_WR, the value of this register sets the starting address for the data
location being written to or read from. When this register is written, the current address pointer
CPU_CP is also updated with the same value. The first read or write from/to the I2C_ BUF register
starts at this address. The location of the data in subsequent read or writes is determined by the
CPU_CP register value, which auto increments after each read or write. Firmware makes certain that
the slave device always has valid data or the data is read before overwritten.
Individual Register Names and Addresses:
0,CDh
CPU_BP : 0,CDh
7 6 5 4 3 2 1 0
Access : POR RW : 00
Bit Name CPU Base Pointer[4:0]
Bit Name Description
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