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PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
Internal Main Oscillator (IMO)
7.3
Register Definitions
The following registers are associated with the Internal Main Oscillator (IMO). The register descriptions have associated reg-
ister tables showing the bit structure for that register. The bits in the tables that are grayed out are reserved bits and are not
detailed in the register descriptions that follow. Always write reserved bits with a value of ‘0’. For a complete table showing all
oscillator registers, refer to the
Summary Table of the Core Registers on page 24
7.3.1
IMO_TR Register
The Internal Main Oscillator Trim Register (IMO_TR) manu-
ally centers the oscillator's output to a target frequency.
This register is loaded with a factory trim value at boot.
When changing frequency ranges, the matching frequency
trim value must be loaded into this register.
A TableRead command to the Supervisory ROM returns the
trim values to the SRAM.
has information on the location of various trim set-
tings stored in Flash tables. Firmware needs to read the
right trim value for desired frequency and update the
IMO_TR register. The IMO_TR register must be changed at
the lower frequency range setting.
For additional information, refer to the
7.3.2
IMO_TR1 Register
The Internal Main Oscillator Trim Register 1 (IMO_TR1)
adjusts the IMO frequency .
Bits 2 to 0: Fine Trim[2:0].
These bits provide a fine tun-
ing capability to the IMO trim. These three bits are the 3 LSB
of the IMO trim with the IMO_TR register supplying the 8
MSB. A larger value in this register will increase the speed
of the oscillator. The value in these bits varies the IMO fre-
quency: approximately 7.5 kHz/step. When the EnableLock
bit is set in the USB_CR1 register, firmware writes to this
register are disabled.
For additional information, refer to the
.
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Access
1,E8h
Trim[7:0]
RW : 00
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Access
1,FAh
Fine Trim[2:0]
RW : 0
Summary of Contents for PSoC CY8CTMG20 Series
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