PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
135
16. System Resets
This chapter discusses the System Resets and their associated registers. PSoC devices support several types of resets. The
various resets are designed to provide error-free operation during power up for any voltage ramping profile, to allow for user
supplied external reset, and to provide recovery from errant code operation. For a complete table of the System Reset regis-
ters, refer to the
Summary Table of the System Resource Registers on page 106
. For a quick reference of all PSoC registers
in address order, refer to the
Register Reference chapter on page 187
.
16.1
Architectural Description
When reset is initiated, all registers are restored to their
default states. In the
, this is indicated by the POR row in the register
tables and elsewhere it is indicated in the Access column
values on the right side of the colon, in the register tables.
Minor exceptions are explained ahead.
The following types of resets occur in the PSoC device:
■
Power on Reset (POR).
This occurs at low supply volt-
age and is comprised of multiple sources.
■
External Reset (XRES).
This active high reset is driven
into the PSoC device on parts that contain an XRES pin.
■
Watchdog Reset (WDR).
This optional reset occurs
when the watchdog timer expires before being cleared
by user firmware. Watchdog resets default to off.
■
Internal Reset (IRES).
This occurs during the boot
sequence if the SROM code determines that Flash
reads are invalid.
The occurrence of a reset is recorded in the Status and
Control registers (CPU_SCR0 for POR, XRES, and WDR)
or in the System Status and Control Register 1 (CPU_SCR1
for IRESS). Firmware can interrogate these registers to
determine the cause of a reset.
16.2
Pin Behavior During Reset
Power on Reset and External Reset cause toggling on two
GPIO pins, P1[0] and P1[1], as described ahead and illus-
trated in
Figure 16-2
. This allows program-
mers to synchronize with the PSoC device. All other GPIO
pins are placed in a high impedance state during and imme-
diately following reset.
16.2.1
GPIO Behavior on Power Up
At power up, the internal POR causes P1[0] to initially drive
a strong high (1) while P1[1] drives a resistive low (0). After
256 sleep oscillator cycles (approximately 8 ms), the P1[0]
signal transitions to a resistive low state. After an additional
256 sleep oscillator clocks, both pins transition to a high
impedance state and normal CPU operation begins. This is
illustrated in the following figure.
Figure 16-1. P1[1:0] Behavior on Power Up
Internal
Reset
P1[0]
P1[1]
HiZ
HiZ
Vdd
POR Trip
Point
S1
R0
R0
R0
T1
T2
T1 = T2 = 256 Sleep Clock Cycles
(approximately 8 ms)
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