Cypress PSoC CY8CTMG20 Series, Technical Reference Manual

Page: 205 / 308

PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C 205
CMP_RDC
0,78h
21.3.18 CMP_RDC
Comparator Read/Clear Register
This register is used to read the state of the comparator data signal and the latched state of the comparator.
In the table above, reserved bits are grayed table cells and are not described in the bit description section below. Reserved
bits must always be written with a value of ‘0’. For additional information, refer to the
Register Definitions on page 103 in the
Comparators chapter.
5 CMP1D Read only bit that returns the dynamically changing state of comparator 1. This bit reads zero when-
ever the comparator is disabled.
4 CMP0D Read only bit that returns the dynamically changing state of comparator 0. This bit reads zero when-
ever the comparator is disabled.
1 CMP1L This bit reads the latch output for comparator 1. It is cleared by either a write of ‘0’ to this bit, or by a
rising edge of the comparator 0 LUT, depending on the state of the CRST1 bit in the CMP_CR1 reg-
ister.
0 CMP0L This bit reads the latch output for comparator 0. It is cleared by either a write of ‘0’ to this bit, or by a
rising edge of the comparator 1 LUT, depending on the state of the CRST0 bit in the CMP_CR1 reg-
ister.
Individual Register Names and Addresses:
CMP_RDC : 0,78h 0,78h
7 6 5 4 3 2 1 0
Access : POR R : 0 R : 0 RC : 0 RC : 0
Bit Name CMP1D CMP0D CMP1L CMP0L
Bit Name Description
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