Cypress PSoC CY8CTMG20 Series, Technical Reference Manual

Page: 217 / 308

PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C 217
CS_STAT
0,A6h
21.3.29 CS_STAT
TrueTouch Status Register
This register controls the TrueTouch counter options.
Never modify the interrupt mask bits while the block is enabled. If a modification to bits 3 to 0 is necessary while the block is
enabled, then pay close attention to ensure that the status bits 7 to 4, are not accidentally cleared. You do this by writing a ‘1’
to all of the status bits when writing to the mask bits. For additional information, refer to the
Register Definitions on page 92 in
the TrueTouch Module chapter .
7 INS Input Status.
0
No event detected.
1 A rising edge on the selected input was detected. Cleared by writing a ‘0’ to this bit.
6 COLS Counter Carry Out Low Status.
0
No event detected.
1 A carry out from low byte counter was detected. Cleared by writing a ‘0’ back to this bit.
5 COHS Counter Carry Out High Status.
0
No event detected.
1 A carry out from high byte counter was detected. Cleared by writing a ‘0’ back to this bit.
4 PPS Pulse Width/Period Measurement Status.
0
No event detected.
1 A pulse width or period measurement was completed. Cleared by writing a ‘0’ back to this
bit.
3 INM Input Interrupt/Mask.
0
Disabled.
1 Input event is enabled to assert the block interrupt.
2 COLM Counter Carry Out Low Interrupt Mask.
0
Disabled.
1 Counter carry out low is enabled to assert the block interrupt.
1 COHM Counter Carry Out High Interrupt Mask.
0
Disabled.
1 Counter carry out high is enabled to assert the block interrupt.
0 PPM Pulse Width/Period Measurement Interrupt Mask.
0
Disabled.
1 Completion of a pulse width or period measurement is enabled to assert the block interrupt.
Individual Register Names and Addresses:
0,A6h
CS_STA
T : 0,A6h
7 6 5 4 3 2 1 0
Access : POR RC : 0 RC : 0 RC : 0 RC : 0 RW : 0 RW : 0 RW : 0 RW : 0
Bit Name INS COLS COHS PPS INM COLM COHM PPM
Bit Name Description
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