PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
59
General Purpose I/O (GPIO)
6.2
Register Definitions
The following registers are associated with the General Purpose I/O (GPIO) and are listed in address order. The register
descriptions have an associated register table showing the bit structure for that register. The bits in the tables that are grayed
out are reserved bits and are not detailed in the register descriptions that follow. Always write reserved bits with a value of 0.
For a complete table of General Purpose I/O registers, refer to the
Core Register Summary on page 24
For a selected GPIO block, the individual registers are addressed in the
Core Register Summary on page 24
. In the register
names, the ‘x’ is the port number, configured at the PSoC device level (x = 0 to 4 typically). All register values are readable,
except for the PRTxDR register; reads of this register return the pin state instead of the register bit state.
6.2.1
PRTxDR Registers
The Port Data Register (PRTxDR) allows for write or read
access of the current logical equivalent of the voltage on the
pin.
Bits 7 to 0: Data[7:0].
Writing the PRTxDR register bits set
the output drive state for the pin to high (for Data = 1) or low
(Data = 0), unless a bypass mode is selected (see
).
Reading the PRTxDR register returns the actual pin state,
as seen by the input buffer. This may not be the same as the
expected output state, if the load pulls the pin more strongly
than the pin’s configured output drive. See
for a detailed discussion of digital I/O.
For additional information, refer to the
6.2.2
PRTxIE Registers
The Port Interrupt Enables (PRTxIE) registers enable or dis-
able interrupts from individual GIPIO pins.
Bits 7 to 0: InterruptEnables[7:0].
These bits enable the
corresponding port pin interrupt. Only four LSB pins are
used since this port has four pins.
‘0’ is port pin interrupt disabled for the corresponding pin.
‘1’ is port pin interrupt enabled for the corresponding pin.
Interrupt mode is determined by the IOINT bit in the
register.
For additional information, refer to the
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Access
0,xxh
Data[7:0]
RW : 00
LEGEND
xx An “x” after the comma in the address field indicates that there are multiple instances of the register. For an expanded address listing of these registers,
refer to the
Core Register Summary on page 24
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Access
0,xxh
InterruptEnables[7:0]
RW : 00
LEGEND
xx An “x” after the comma in the address field indicates that there are multiple instances of the register. For an expanded address listing of these registers,
refer to the
Summary of Contents for PSoC CY8CTMG20 Series
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