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PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
General Purpose I/O (GPIO)
Interrupt High mode. If the last value read from the GPIO
was ‘1’, the GPIO is in Interrupt Low mode.
assumes that the GIE is set, GPIO interrupt mask
is set, and that the IOINT bit was set to high. The Change
Interrupt mode relies on the value of an internal read register
to determine if the pin state changed. Therefore, the port
that contains the GPIO in question must be read during
every interrupt service routine. If the port is not read, the
Interrupt mode acts as if it is in high mode when the latch
value is ‘0’ and low mode when the latch value is ‘1’.
Figure 6-3. GPIO Interrupt Mode IOINT = 1
6.1.7
Data Bypass
GPIO pins are configured to either output data through CPU
writes to the PRTxDR registers or to bypass the port's data
register and output data from internal functions instead. The
bypass path is shown in
which is selected by the Alt Select input. These data bypass
options are selected in one of two ways.
■
For internal functions such as I2C and SPI, the hardwire
automatically selects the bypass mode for the required
pins when the function is enabled. In addition, some
bypass outputs are selected by the user through the
OUT_P1 register. For these, the pin is configured for
data bypass when the register bit is set high, which
allows an internal signal to be driven to the pin.
■
For all bypass modes, the wanted drive mode of the pin
must be configured separately for each pin, with the
PRTxDM1 and PRTxDM0 registers.
Table 6-1. GPIO Interrupt Modes
IE
IOINT
Description
0
0
Bit interrupt disabled, INTO deasserted
0
1
Bit interrupt disabled, INTO d-asserted
1
0
Assert INTO when PIN = low
1
1
Assert INTO when PIN = change from last read
Last Value Read From Pin was ‘0’
Pin State
Waveform
Interrupt
Occurs
(a)
Pin State Waveform
GPIO Pin
Interrupt Enable
Set
Interrupt
Occurs
(b)
GPIO Pin
Interrupt Enable
Set
Last Value Read From Pin was ‘1’
Pin State
Waveform
GPIO Pin
Interrupt Enable
Set
Interrupt
Occurs
(c)
Pin State
Waveform
GPIO Pin
Interrupt
Enable Set
Interrupt
Occurs
(d)
Summary of Contents for PSoC CY8CTMG20 Series
Page 4: ...4 Contents Overview Feedback...
Page 26: ...26 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C Section B PSoC Core Feedback...
Page 82: ...82 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C Sleep and Watchdog Feedback...
Page 134: ...134 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C I2C Slave Feedback...
Page 142: ...142 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C System Resets Feedback...
Page 160: ...160 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C SPI Feedback...
Page 182: ...182 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C Full Speed USB Feedback...
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