PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
189
PRTxIE
0,01h
21.3.2
PRTxIE
Port Interrupt Enable Registers
These registers enable or disable interrupts from individual GPIO pins.
The upper nibble of the PRT4IE register returns the last data bus value when read and must be masked off before using this
information. For additional information, refer to the
Register Definitions on page 59
in the GPIO chapter.
7:0
Interrupt Enables[7:0]
These bits enable the corresponding port pin interrupt. Only four LSB are used since this port has
four pins.
0
Port pin interrupt disabled for the corresponding pin.
1
Port pin interrupt enabled for the corresponding pin. Interrupt mode is determined by the
IOINT bit in the
register.
Individual Register Names and Addresses:
0,01h
PRT0IE : 0,01h
PRT1IE : 0,05h
PRT2IE : 0,09h
PRT3IE : 0,0Dh
PRT4IE : 0,11h
7
6
5
4
3
2
1
0
Access : POR
RW : 00
Bit Name
Interrupt Enables[7:0]
Bit
Name
Description
Summary of Contents for PSoC CY8CTMG20 Series
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