Cypress PSoC CY8CTMG20 Series, Technical Reference Manual

Page: 272 / 308

272 PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
IO_CFG1
1,DCh
21.4.14 IO_CFG1
Input/Output Configuration Register 1
This register is used to configure the Port 1 output regulator and set the interrupt mode for all GPIO.
In the table above, note that reserved bits are grayed table cells and are not described in the bit description section below.
Reserved bits must always be written with a value of ‘0’. For additional information, refer to the
Register Definitions on
page 59 in the GPIO chapter.
7 StrongP Setting this bit increases the drive strength and edge ratio for high outputs.
5:4 Range[1:0] Selects the high output level for Port 1 outputs.
00
3.0 volts
01 3.0 volts
10 1.8 volts
11 2.5 volts
3 P1-LOW_THRS This bit reduces the threshold voltage of the P1 port input buffers so that there are no compatibility
issues when Port 1 is communicating at regulated voltage levels.
0
Standard threshold of VIH, VIL
1 Reduce threshold of VIH, VIL
2 SPICLK_ON_P10 When set to ‘1’, the SPI clock is mapped to Port 1 pin 0. Otherwise, it is mapped to Port 1 pin 3.
1 REG_EN Controls the regulator on Port 1 outputs.
0
Regulator disabled, so Port 1 strong outputs drive to Vdd.
1 Regulator enabled, so Port 1 strong outputs drive to approximately 3V (for Vdd > 3V).
0 IO INT Sets the GPIO interrupt mode for all pins in the PSoC device. GPIO interrupts are also controlled at
each pin by the PRTxIE registers, and by the global GPIO bit in the INT_MSK0 register.
0
GPIO interrupt configured for interrupt when pin is low.
1 GPIO interrupt configured for interrupt when pin state changes from last time port was read.
Individual Register Names and Addresses:
1,DCh
IO_CFG1 : 1,DCh
7 6 5 4 3 2 1 0
Access : POR RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0
Bit Name
StrongP Range[1:0]
P1_LOW_
THRS
SPICLK_
ON_P10
REG_EN IO INT
Bits Name Description
[+] Feedback