PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
RAM Paging
4.2.3
STK_PP Register
The Stack Page Pointer Register (STK_PP) is used to set
the effective SRAM page for stack memory accesses in a
multi-SRAM page PSoC device.
Bits 2 to 0: Page Bits[2:0].
These bits have the potential
to affect two types of memory access.
The purpose of this register is to determine on which SRAM
page to store the stack. In the reset state, this register's
value is 0x00 and the stack is in SRAM Page 0. However, if
the STK_PP register value is changed, the next stack opera-
tion occurs on the SRAM page indicated by the new
STK_PP value. Therefore, set the value of this register early
in the program and never change it. If the program changes
the STK_PP value after the stack grows, the program must
ensure that the STK_PP value is restored when needed.
Note
The impact that the STK_PP register has on the stack
is independent of the SRAM Paging bits in the CPU_F regis-
ter.
The second type of memory accesses that the STK_PP reg-
ister affects are indexed memory accesses when the
CPU_F[7:6] bits are set to 11b. In this mode, Source
Indexed and Destination Indexed memory accesses are
directed to the stack SRAM page, rather than the SRAM
page indicated by the IDX_PP register or SRAM Page 0.
For additional information, refer to the
4.2.4
IDX_PP Register
The Index Page Pointer Register (IDX_PP) sets the effective
SRAM page for indexed memory accesses in a multi-SRAM
page PSoC device.
Bits 2 to 0: Page Bits[2:0].
These bits allow instructions,
which use the Source Indexed and Destination Indexed
address modes, to operate on an SRAM page that is not
equal to the current SRAM page. However, the effect this
register has on indexed addressing modes is only enabled
when the CPU_F[7:6] is set to 10b.
When CPU_F[7:6] is set to 10b and an indexed memory
access is made, the access is directed to the SRAM page
indicated by the value of the IDX_PP register.
See the STK_PP register description for more information
on other indexed memory access modes. For additional
4.2.5
MVR_PP Register
The MVI Read Page Pointer Register (MVR_PP) sets the
effective SRAM page for MVI read memory accesses in a
multi-SRAM page PSoC device.
Bits 2 to 0: Page Bits[2:0].
These bits are only used by
the
MVI A, [expr]
instruction, not to be confused with the
MVI [expr], A
instruction covered by the MVW_PP reg-
ister. This instruction is considered a read because data is
transferred from SRAM to the microprocessor's A register
(CPU_A).
When an
MVI A, [expr]
instruction is executed in a
device with more than one page of SRAM, the SRAM
address that is read by the instruction is determined by the
value of the least significant bits in this register. However,
the pointer for the
MVI A, [expr]
instruction is always
located in the current SRAM page. See the
PSoC Designer
Assembly Language User Guide
for more information on the
MVI A, [expr]
instruction.
The function of this register and the
MVI
instructions are
independent of the SRAM Paging bits in the CPU_F register.
For additional information, refer to the
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Access
0,D1h
Page Bits[2:0]
RW : 0
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Access
0,D3h
Page Bits[2:0]
RW : 0
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Access
0,D4h
Page Bits[2:0]
RW : 0
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