220
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
PRS_CR
0,A9h
21.3.32 PRS_CR
Pseudo Ransom Sequence and Prescaler Control Register
This register controls the Prescaler and Pseudo Random Sequence generator output. For additional information, refer to the
Register Definitions on page 92
in the TrueTouch Module chapter
.
7
CS_CLK_OUT
This bit selects the TrueTouch clock (inversion or non-inversion depending on bit 6 setting) to be
routed onto primary pin depending on the OUT_P1/OUT_P0 register selection.
1
Route prescaler output or PRS output depending on CSD_PRSCLK in CS_CR0 when in
CSD mode, or route clock based on CLKSEL bits in CS_CR1 register in normal TrueTouch
mode to primary pins P1[2]/P0[7] depending on OUT_P1/OUT_P0 bit selections instead of
normal CSOUT[ selections. See OUT_P1/OUT_P0 registers for details.
0
Use CSOUT [1:0] selections as normal.
6
CS_CLK_INV
This bit allows you to route either TrueTouch clock or inversion of the TrueTouch clock onto pin.
1
Inverted TrueTouch clock routes to pin (see bit 7).
0
Non-inverted TrueTouch clock routes to pin (see bit 7).
5
PRS_12BIT
This bit allows selection between 8-bit PRS or 12-bit PRS output.
0
MSB of 8-bit PRS is sent out.
1
MSB of 12-bit PRS is sent out
4
PRS_EN
This bit is used to enable or disable the PRS block.
0
PRS is disabled. PRS block output is '0'.
1
PRS is enabled and the bit 5 decides whether MSB of 12-bit PRS is sent out or MSB of 8-bit
PRS is sent out.
3
PRESCALEBYP
This bit is used to bypass the prescaler and pass the input clock undivided onto the output. The out-
put of the prescaler feeds the clock input to the PRS block.
0
Divided clock is sent out of prescaler depending on bit [2:0] setting.
1
Incoming IMO clock is sent out of prescaler without any division.
2:0
PRESCALE_CLK_DIV[2:0]
These bits allow for of one of eight frequencies of incoming IMO clock to be fed as input to PRS.
000
Divides the input IMO clock by 2.
001
Divides the input IMO clock by 4.
010
Divides the input IMO clock by 8.
011
Divides the input IMO clock by 16.
100
Divides the input IMO clock by 32.
101
Divides the input IMO clock by 64.
110
Divides the input IMO clock by 128.
111
Divides the input IMO clock by 256.
Individual Register Names and Addresses:
0,A9h
PRS_CR : 0,A9h
7
6
5
4
3
2
1
0
Access : POR
RW : 0
RW : 0‘
RW : 0‘
RW : 0
RW : 0
RW : 0
Bit Name
CS_CLK_OUT
CS_CLK_INV
PRS_12BIT
PRS_EN
PRESCALE-
BYP
PRESCALE_CLK_DIV[2:0]
Bit
Name
Description
Summary of Contents for PSoC CY8CTMG20 Series
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