Cypress PSoC CY8CTMG20 Series, Technical Reference Manual

Page: 104 / 308

104 PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
Comparators
13.2.3 CMP_CR0 Register
The Comparator Control Register 0 (CMP_CR0) enables
and configures the input range of the comparators.
Bit 4: CMP1EN. This bit enables comparator 1.
Bit 0: CMP0EN.
This bit enables comparator 0.
For additional information, refer to the CMP_CR0 register on
page 207 .
13.2.4 CMP_CR1 Register
The Comparator Control Register 1 (CMP_CR1) config-
ures the comparator output options.
Bit 7: CINT1. This bit connects the comparator 1 output
to the analog output.
Bit 6: CPIN1. This bit selects whether the comparator 1
LUT output or the latched output is routed to a GPIO pin.
Bit 5: CRST1. This bit selects whether the comparator 1
latch is reset upon a register write or by a rising edge from
the comparator 0 LUT output.
Bit 4: CDS1. This bit selects between the comparator 1
LUT and the latched output for the main comparator out-
put that drives to the capacitive sense and interrupt logic.
Bit 3: CINT0. This bit connects the comparator 0 output
to the analog output.
Bit 2: CPIN0. This bit selects whether the comparator 0
LUT output or the latched output is routed to a GPIO pin.
Bit 1: CRST0. This bit selects whether the comparator 0
latch is reset upon a register write or by a rising edge from
the comparator 1 LUT output.
Bit 0: CDS0.
This bit selects between the comparator 0
LUT and the latched output for the main comparator out-
put that drives to the capacitive sense and interrupt logic.
For additional information, refer to the CMP_CR1 register on
page 208 .
13.2.5 CMP_LUT Register
The Comparator LUT Control Register (CMP_LUT) selects
the logic function.
Bits 7 to 4: LUT1[3:0]. These bits control the selection of
the LUT 1 logic functions that may be selected for the com-
parator channel 1.
Bits 3 to 0: LUT0[3:0]. These bits control the selection of
LUT 0 logic functions that may be selected for the compara-
tor channel 0. The selections are shown in the following
table:
For additional information, refer to the CMP_LUT register on
page 210 .
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access
0,7Ah CMP_CR0 CMP1EN CMP0EN RW : 00
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access
0,7Bh CMP_CR1 CINT1 CPIN1 CRST1 CDS1 CINT0 CPIN0 CRST0 CDS0 RW : 00
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access
0,7Ch CMP_LUT LUT1[3:0] LUT0[3:0] RW : 00
LUTx[3:0]
0h: 0000: FALSE
1h: 0001: A .AND. B
2h: 0010: A .AND. B
3h: 0011: A
4h: 0100: A .AND. B
5h: 0101: B
6h: 0110: A .XOR. B
7h: 0111: A .OR. B
8h: 1000: A .NOR. B
9h: 1001: A .XNOR. B
Ah: 1010: B
Bh: 1011: A .OR. B
Ch: 1100: A
Dh: 1101: A .OR. B
Eh: 1110: A. NAND. B
Fh: 1111: TRUE
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