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PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
CUR_PP
0,D0h
21.3.46 CUR_PP
Current Page Pointer Register
This register is used to set the effective SRAM page for normal memory accesses in a multi-SRAM page device. It is only
used when a device has more than one SRAM page.
In the table above, note that reserved bits are grayed table cells and are not described in the bit description section below.
Reserved bits must always be written with a value of ‘0’. For additional information, refer to the
in the RAM Paging chapter
.
2:0
Page Bits[2:0]
Bits determine which SRAM page is used for generic SRAM access. See the
for more information.
000b
SRAM Page 0
001b
SRAM Page 1
010b
SRAM Page 2
011b
SRAM Page 3
100b
SRAM Page 4
101b
SRAM Page 5
110b
SRAM Page 6
111b
SRAM Page 7
Individual Register Names and Addresses:
0,D0h
CUR_PP : 0,D0h
7
6
5
4
3
2
1
0
Access : POR
RW : 0
Bit Name
Page Bits[2:0]
Bit
Name
Description
Summary of Contents for PSoC CY8CTMG20 Series
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