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PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
SLP_CFG2
1,ECh
21.4.25 SLP_CFG2
Sleep Configuration Register 2
This register holds the configuration for I2C sleep, deep sleep, and buzz.
In the table above, note that reserved bits are grayed table cells and are not described in the bit description section below.
Reserved bits must always be written with a value of ‘0’. For additional information, refer to the
in the Sleep and Watchdog chapter.
3:2
ALT_Buzz[1:0]
These bits control additional selections for POR/LVD buzz rates.
00
Compatibility mode, buzz rate is determined by PSSDC bits.
01
Duty cycle is 1/32768.
10
Duty cycle is 1/8192.
11
Reserved.
1
I2C_ON
This bit enables the standby regulator in I2C sleep mode at a level sufficient to supply the I2C cir-
cuitry.
0
LSO_OFF
This bit disables the LSO oscillator when in sleep state.
Individual Register Names and Addresses:
1,ECh
SLP_CFG2 : 1,ECh
7
6
5
4
3
2
1
0
Access : POR
RW : 0
RW : 0
RW : 0
Bit Name
ALT_Buzz[1:0]
I2C_ON
LSO_OFF
Bit
Name
Description
Summary of Contents for PSoC CY8CTMG20 Series
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