Cypress PSoC CY8CTMG20 Series, Technical Reference Manual

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42 PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
RAM Paging
4.2 Register Definitions
The following registers are associated with RAM Paging and are listed in address order. The register descriptions have an
associated register table showing the bit structure for that register. The bits in the tables that are grayed out are reserved bits
and are not detailed in the register descriptions that follow. Always write reserved bits with a value of ‘0‘. For a complete table
of RAM Paging registers, refer to the
Summary Table of the Core Registers on page 24 .
4.2.1 TMP_DRx Registers
The Temporary Data Registers (TMP_DR0, TMP_DR1,
TMP_DR2, and TMP_DR3) enhance the performance in
multiple SRAM page PSoC devices.
These registers have no predefined function (for example,
the compiler and hardware do not use these registers) and
exist for the user to define.
Bits 7 to 0: Data[7:0]. Due to the paged SRAM architec-
ture of PSoC devices with more than 256 bytes of SRAM, a
value in SRAM is not always accessible without first chang-
ing the current page. The TMP_DRx registers are readable
and writable registers that are provided to improve the per-
formance of multiple SRAM page PSoC devices, by supply-
ing some register space for data that is always accessible.
For an expanded listing of the TMP_DRx registers, refer to
the
Summary Table of the Core Registers on page 24 . For
additional information, refer to the TMP_DRx register on
page 266 .
4.2.2 CUR_PP Register
The Current Page Pointer Register (CUR_PP) sets the
effective SRAM page for normal memory accesses in a
multi-SRAM page PSoC device.
Bits 2 to 0: Page Bits[2:0]. These bits affect the SRAM
page that is accessed by an instruction when the
CPU_F[7:6] bits have a value of either 10b or 11b. Source
Indexed, Destination Indexed addressing modes, and stack
instructions, are never affected by the value of the CUR_PP
register. (See the STK_PP and IDX_PP registers for more
information.)
The Source Indirect Post Increment and Destination Indirect
Post Increment addressing modes, better know as
MVI , are
only partially affected by the value of the CUR_PP register.
For
MVI
instructions, the pointer address is in the SRAM
page indicated by CUR_PP, but the address pointed to may
be in another SRAM page.
See the MVR_PP and MVW_PP register descriptions for
more information.
For additional information, refer to the CUR_PP register on
page 234 .
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access
x,6xh TMP_DRx Data[7:0] RW : 00
LEGEND
x An ‘x’ before the comma in the address field indicates that this register can be read or written to no matter what bank is used. An “x” after the comma in the
address field indicates that there are multiple instances of the register.
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access
0,D0h CUR_PP Page Bits[2:0] RW : 00
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