PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
283
SLP_CFG
1,EBh
21.4.24 SLP_CFG
Sleep Configuration Register
This register sets up the sleep duty cycle.
In the table above, note that reserved bits are grayed table cells and are not described in the bit description section below.
Reserved bits must always be written with a value of ‘0’. For additional information, refer to the
in the Sleep and Watchdog chapter.
7:6
PSSDC[1:0]
Sleep Duty Cycle. Controls the ratios (in numbers of 32.768 kHz clock periods) of “on” time versus
“off” time for PORLVD, bandgap reference, and pspump.
00b
1 / 256 (8 ms).
01b
1 / 1024 (31.2 ms).
10b
1 / 64 (2 ms).
11b
1 / 16 (500 µs).
Individual Register Names and Addresses:
1,EBh
SLP_CFG : 1,EBh
7
6
5
4
3
2
1
0
Access : POR
RW : 0
Bit Name
PSSDC[1:0]
Bit
Name
Description
Summary of Contents for PSoC CY8CTMG20 Series
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