PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
117
15. I
2
C Slave
This chapter explains the I
2
C Slave block and its associated registers. The I
2
C communications block is a serial processor
designed to implement a complete I
2
C slave. For a complete table of the I
2
C registers, refer to the
tem Resource Registers on page 106
. For a quick reference of all PSoC registers in address order, refer to the
.
15.1
Architectural Description
The I
2
C slave enhanced communications block is a serial-to-parallel processor, designed to interface the PSoC device to a
two-wire I
2
C serial communications bus. To eliminate the need for excessive CPU intervention and overhead, the block pro-
vides I
2
C-specific support for status detection and generation of framing bits. By default, the I
2
C Slave Enhanced module is
firmware compatible with the previous generation of I
2
C slave functionality. However, this module provides new features that
are configurable to implement significant flexibility for both internal and external interfacing.
Figure 15-1. I
2
C Block Diagram
Basic I
2
C features include:
■
Slave, transmitter, and receiver operation
■
Byte processing for low CPU overhead
■
Interrupt or polling CPU interface
■
Support for clock rates of up to 400 kHz
■
7- or 10-bit addressing (through firmware support)
■
SMBus operation (through firmware support)
Enhanced features of the I
2
C Slave Enhanced module
include:
■
Support for 7-bit hardware address compare
■
Flexible data buffering schemes
■
A "no bus stalling" operating mode
■
A low power bus monitoring mode
I2C Core
I2C Basic
Configuration
I2C_CFG
I2C_SCR
I2C_DR
Plus Features
HW Addr Cmp
Buffer Module
CPU Port
Buffer Ctl
32 Byte RAM
I2C Plus
Slave
I2C_ADDR
SDA_OUT
SCL_IN
SYSCLK
I2C_EN
To/From
GPIO
Pins
STANDBY
SCL_OUT
SDA_IN
I2C_XSTAT
I2C_XCFG
I2C_BUF
I2C_BP
I2C_CP
MCU_CP
MCU_BP
Sy
ste
m
B
us
Summary of Contents for PSoC CY8CTMG20 Series
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