PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
169
Full-Speed USB
(Self-powered devices do not need to go into Suspend
mode.) This condition is detected by monitoring the Bus
Activity bit in the USB_CR1 register. This bit must be polled
periodically. If it reads high (bus activity present), it must be
cleared by firmware. If no activity is detected for the desired
time (for example, 3 ms), then the device must enter Sus-
pend mode.
Not all sleep modes preserve the USB configuration register
states during sleep. The Standby I2C-USB mode is the pre-
ferred sleep mode for USB operation because the state of
all USB registers is maintained during sleep. The other
sleep modes do not preserve all of these registers to save
sleep power.
The USB regulator settings must not be changed when
entering sleep state, since the regulator automatically enters
a low power state for the given regulator mode (pass-
through or regulating).
20.2.5.1
Using Standby I2C-USB Sleep Mode
for USB Suspend
To enter Standby I2C-USB mode, firmware powers down
the desired functions, as it would to enter a Standby I2C-
USB mode sleep state as documented in
trol Implementation Logic on page 74
, including writing the
SLEEP bit of the CPU_SCR0 register. In this mode, USB
configuration registers and data are preserved during sleep.
20.2.5.2
Using Standby or Deep Sleep Modes
for USB Suspend
The Standby and Deep Sleep modes do not have hardware
supported for USB suspend operation because not all USB
registers are preserved in these modes. In USB parts, if
there is a need to enter Standby or Deep Sleep mode, then
user firmware must save the non-retained registers to
SRAM before entering into sleep and restore these registers
once the device wakes up. The list of these registers is
given below. Some configuration registers retain their val-
ues in all sleep modes: USB_CR0, USB_CR1, USBIO_CR0,
USBIO_CR1, IMO_TR, IMO_TR1. In addition, the USB
SRAM contents are preserved in all sleep modes.
The USB registers that retain state in Standby I2C-USB
mode but not in other sleep modes are: the endpoint control
registers (EPx_CRx), endpoint PMA write address
(PMAx_WA)/read address (PMAx_RA) registers, PMA data
registers (PMAx_DR), endpoint count registers
(EPx_CNTx), endpoint 0 data register (EP0_DRx) and start
of frame registers (USB_SOFx). These registers are reset
after the device comes out of sleep.
(An alternative is to simply disconnect from the USB bus
before going into one of these sleep modes, and then re-
connect to re-initialize the USB system after waking up.)
20.2.5.3
Wakeup from Suspend
The USB wake interrupt must be enabled to allow the device
to exit the sleep state when there is activity on the USB bus.
This interrupt can be enabled at any time since it only
asserts when the device is in the sleep state. Other inter-
rupts may be optionally enabled, such as the sleep interrupt,
GPIO, I2C, to periodically wake the device while in USB
suspend state. The USB wake interrupt can wake up the
device from all the three sleep states (Standby sleep, I2C-
USB sleep and Deep Sleep). If D+ is low when the SLEEP
bit is being set, the device briefly enters sleep state, and
then exits sleep due to the USB wake interrupt.
By carefully using a sleep timer interrupt, the device can
wake periodically, monitor the environment, and return to
sleep while maintaining a low average current that meets
the USB suspend current specification.
If the device needs to issue a resume signal to the USB sys-
tem, firmware can write to the TEN and TD bits in the
USBIO_CR0 register to manually force a K state on the bus.
Using these bits produces signaling that meets the USB tim-
ing specifications.
When driving a resume, the J state (TD=1) must be driven
briefly before driving the K state (TD=0). The steps are sum-
marized as follows:
1. Drive the J state (TEN=1, TD=1) for one instruction.
2. Drive the resume, or K state (TEN=1, TD=0) for the
proper time (1 ms to 15 ms).
3. Stop driving the USB bus manually (TEN=0).
20.2.6
Regulator
The transceiver contains a built-in regulator that can be
used to power the transceiver from the USB bus voltage or
other supply around 5V. The regulator supplies the proper
levels for USB signals, which switch between 0V and 3.3V
nominally. If the PSoC device is operating with a Vdd supply
near 3.3V, then the regulator must be placed into a pass-
through mode so that the Vdd voltage is directly supplied to
the transceiver, without regulation. The RegEnable bit (bit 0
in the USB_CR1 register) is used to pick between the regu-
lating mode (5V supply) or the passthrough mode (3.3V sup-
ply). At power up, the regulator is automatically held in pass-
through mode, but the USB transceiver pins are tristated.
Summary of Contents for PSoC CY8CTMG20 Series
Page 4: ...4 Contents Overview Feedback...
Page 26: ...26 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C Section B PSoC Core Feedback...
Page 82: ...82 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C Sleep and Watchdog Feedback...
Page 134: ...134 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C I2C Slave Feedback...
Page 142: ...142 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C System Resets Feedback...
Page 160: ...160 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C SPI Feedback...
Page 182: ...182 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C Full Speed USB Feedback...
Page 302: ...302 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C Glossary Feedback...
