PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
241
I2C_DR
0,D8h
21.3.53 I2C_DR
I
2
C Data Register
This register provides read/write access to the Shift register.
This register is read only for received data and write only for transmitted data. For additional information, refer to the
in the I2C Slave chapter
.
7:0
Data[7:0]
Read received data or write data to transmit.
Individual Register Names and Addresses:
0,D8h
I2C_DR : 0,D8h
7
6
5
4
3
2
1
0
Access : POR
RW : 00
Bit Name
Data[7:0]
Bit
Name
Description
Summary of Contents for PSoC CY8CTMG20 Series
Page 4: ...4 Contents Overview Feedback...
Page 26: ...26 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C Section B PSoC Core Feedback...
Page 82: ...82 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C Sleep and Watchdog Feedback...
Page 134: ...134 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C I2C Slave Feedback...
Page 142: ...142 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C System Resets Feedback...
Page 160: ...160 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C SPI Feedback...
Page 182: ...182 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C Full Speed USB Feedback...
Page 302: ...302 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C Glossary Feedback...