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PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
I2C Slave
15.3.5
I2C_CP Register
The I
2
C Current Address Pointer Register (I2C_CP) con-
tains the current address value of the RAM data buffer.
Note
When in compatibility mode, this register is not in use.
Bits 4 to 0: I2C Current Pointer[4:0].
This register gets
set at the same time and with the same value as the
. After each completed data byte of the current I
2
C
transaction, the value of this register is incremented by one.
The value rolls over to 0x00 when the master writes the
32nd byte.
The value of this register always determines the location
that read or write data comes from or is written to. This reg-
ister is set to the value contained in the
on
every start condition detected in the bus.
For additional information, refer to the
.
15.3.6
CPU_BP Register
The CPU Base Address Pointer Register (CPU_BP) con-
tains the base address value of the RAM data buffer.
Note
When in compatibility mode, this register is not in use.
Bits 4 to 0: CPU Base Pointer[4:0].
This register value is
completely controlled by I/O writes by the CPU. Firmware
routines must set this register. As with the I2C_BP, the value
of this register sets the starting address for the data location
being written or read. When this register is written, the cur-
rent address pointer, CPU_CP, is also updated with the
same value.
The first read or write from/to the I2C_ BUF register start at
this address. The location of the data in subsequent read or
writes is determined by the CPU_CP register value, which
auto increments after each read or write. Firmware makes
certain that the slave device always has valid data or the
data is read before overwritten.
For additional information, refer to the
.
15.3.7
CPU_CP Register
The CPU Current Address Pointer Register (CPU_CP) con-
tains the current address value of the RAM data buffer.
Note
When in compatibility mode, this register is not in use.
Bits 4 to 0: CPU Current Pointer[4:0].
This register is set
at the same time and with the same value as the
. Whenever the
read, the CPU_CP increments automatically.
For additional information, refer to the
.
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Access
0,CCh
I2C Current Pointer[4:0]
R : 00
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Access
0,CDh
CPU Base Pointer[4:0]
RW : 00
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Access
0,CEh
CPU Current Pointer[4:0]
R : 00
Summary of Contents for PSoC CY8CTMG20 Series
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Page 26: ...26 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C Section B PSoC Core Feedback...
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Page 134: ...134 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C I2C Slave Feedback...
Page 142: ...142 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C System Resets Feedback...
Page 160: ...160 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C SPI Feedback...
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