PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
227
I2C_XSTAT
0,C9h
21.3.39 I2C_XSTAT
I
2
C Extended Status Register
This register reads enhanced feature status.
When the bits of the
register are left in their reset state, the block is in compatibility mode and this register is not in
use. In the table above, note that reserved bits are grayed table cells and are not described in the bit description section
below. Always write reserved bits with a value of ‘0’. For additional information, refer to the
Register Definitions on page 122
in the I2C Slave chapter.
1
Dir
This bit indicates the direction of the current transfer. A ’1’ indicates a master read, and a ‘0’ indicates
a master write. It is only valid when the Slave Busy bit (bit 0) is set to a ‘1’.
0
Slave Busy
This bit is set upon a hardware compare and is reset upon the following stop signal. Poll this bit to
determine when the slave is busy and the buffer module is being accessed.
Individual Register Names and Addresses:
0,C9h
0,D0h
I2C_XSTAT : 0,C9h
7
6
5
4
3
2
1
0
Access : POR
R : 0
R : 0
Bit Name
Dir
Slave Busy
Bit
Name
Description
Summary of Contents for PSoC CY8CTMG20 Series
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Page 134: ...134 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C I2C Slave Feedback...
Page 142: ...142 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C System Resets Feedback...
Page 160: ...160 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C SPI Feedback...
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