Cypress PSoC CY8CTMG20 Series, Technical Reference Manual

Page: 114 / 308

114 PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
Digital Clocks
view on page 70 for the proper sequence to enable the
ECO.
Bit 6: Disable Buzz. Setting this bit high causes the band-
gap and POR/LVD systems to remain powered off continu-
ously during sleep. In this case, there is no periodic “buzz”
(brief wakeup) of these functions during sleep. This bit has
no effect when the No Buzz bit is set high.
Bit 5: No Buzz. Normally, when the SLEEP bit is set in the
CPU_SCR register, all PSoCdevice systems are powered
down, including the bandgap reference. However, to facili-
tate the detection of POR and LVD events at a rate higher
than the sleep interval, the bandgap circuit is powered up
periodically (for about 60
μ
s) at the Sleep System Duty
Cycle, which is independent of the sleep interval and typi-
cally higher. When the No Buzz bit is set, the Sleep System
Duty Cycle value is overwritten and the bandgap circuit is
forced to be on during sleep. This results in faster response
to an LVD or POR event (continuous detection as opposed
to periodic), at the expense of higher average sleep current.
Bits 4 and 3: Sleep[1:0]. The available sleep interval
selections are shown in the table below. Sleep intervals are
approximate based upon the accuracy of the internal low
speed oscillator.
Bits 2 to 0: CPU Speed[2:0].
The M8C operates over a
range of CPU clock speeds, allowing you to tailor the M8C’s
performance and power requirements to the application.
The reset value for the CPU speed bits is 010b. Therefore,
the default CPU speed is one-half of the clock source. The
internal main oscillator is the default clock source for the
CPU speed circuit; therefore, the default CPU speed is 6.0
MHz. See
External Clock on page 110 for more information
on the supported frequencies for externally supplied clocks.
The CPU frequency is changed with a write to the
OSC_CR0 register. There are eight frequencies generated
from a power-of-two divide circuit that is selected by a 3-bit
code. At any given time, the CPU 8-to-1 clock mux is select-
ing one of the available frequencies, which is resynchro-
nized to the 24 MHz master clock at the output. The IMO
frequency is also selectable, as discussed in the IMO chap-
ter in the
Architectural Description on page 63 . This offers
an option to lower both system and CPU clock speed to
save power. The selections are shown in the table below
(reset state is 001b).
An automatic protection mechanism is available for systems
that need to run at peak CPU clock speed but cannot guar-
antee a high enough supply voltage for that clock speed.
See the LVDTBEN bit in the
VLT_CMP Register on
page 144 for more information.
Note During USB operation, the CPU speed can be set to
any setting. Be aware that USB throughput decreases with a
decrease in CPU speed. For maximum throughput, the CPU
clock should be made equal to the system clock. The sys-
tem clock must be 24 MHz for USB operation.
For additional information, refer to the OSC_CR0 register on
page 276 .
Sleep Interval
OSC_CR[4:3]
Sleep Timer
Clocks
Sleep Period
(Nominal)
Watchdog Period
(Nominal)
00b (Default) 64 1.95 ms 6 ms
01b 512 15.6 ms 47 ms
10b 4096 125 ms 375 ms
11b 32,768 1 sec 3 sec
Bits
6 MHz
Internal Main
Oscillator
12 MHz
Internal Main
Oscillator
24 MHz
Internal Main
Oscillator
External Clock
000b 750 kHz 1.5 MHz 3 MHz EXTCLK/ 8
001b 1.5 MHz 3.0 MHz 6 MHz EXTCLK/ 4
010b 3 MHz 6.0 MHz 12 MHz EXTCLK/ 2
011b 6 MHz 12.0 MHz 24 MHz EXTCLK/ 1
100b 375 kHz 750 Hz 1.5 MHz EXTCLK/ 16
101b 187.5 kHz 375 kHz 750 kHz EXTCLK/ 32
110b 46.8 kHz 93.7 kHz 187.5 kHz EXTCLK/ 128
111b 23.4 kHz 46.8 kHz 93.7 kHz EXTCLK/ 256
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