144
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
POR and LVD
17.2
Register Definitions
The following registers are associated with the POR and LVD, and are listed in address order. The register descriptions below
have an associated register table showing the bit structure. The bits that are grayed out in the register tables are reserved bits
and are not detailed in the register descriptions that follow. Reserved bits must always be written with a value of ‘0’. For a
complete table of the POR registers, refer to the
Summary Table of the System Resource Registers on page 106
.
17.2.1
VLT_CR Register
The Voltage Monitor Control Register (VLT_CR) sets the trip
points for POR, MON1 and LVD.
The VLT_CR register is cleared by all resets. This can cause
reset cycling during very slow supply ramps to 5V when the
MON1 range is set for the 5V range. This is because the
reset clears the MON1 range setting back to 1.8V and a new
boot or startup occurs (possibly many times). You can man-
age this with sleep mode or reading voltage status bits if
such cycling is an issue.
Bits 5 and 4: PORLEV[1:0].
These bits set the Vcc level
at which PPOR switches to one of three valid values. Do not
use 11b because it is reserved.
See the “DC POR and LVD Specifications” table in the Elec-
trical Specifications section of the PSoC device data sheet
for voltage tolerances for each setting.
Bit 3: LVDTBEN.
This bit is AND’ed with LVD to produce a
throttle back signal that reduces CPU clock speed when low
voltage conditions are detected. When the throttle back sig-
nal is asserted, the CPU speed bits in the OSC_CR0 regis-
ter are reset, forcing the CPU speed to its reset state.
Bits 2 to 0: VM[2:0].
These bits set the Vdd level at which
the LVD Comparator switches.
See the “DC POR and LVD Specifications” table in the Elec-
trical Specifications section of the PSoC device data sheet
for voltage tolerances for each setting.
For additional information, refer to the
.
17.2.2
VLT_CMP Register
The Voltage Monitor Comparators Register (VLT_CMP)
reads the state of internal supply voltage monitors.
Bit 1: LVD.
This bit reads the state of the LVD comparator.
Zero Vdd is above the trip point. The trip points for LVD are
set by VM[2:0] in the VLT_CR register.
For additional information, refer to the
.
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Access
1,E3h
PORLEV[1:0]
LVDTBEN
VM[2:0]
RW : 00
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Access
1,E4h
LVD
RW : 0
Summary of Contents for PSoC CY8CTMG20 Series
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