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PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
VLT_CMP
1,E4h
21.4.21 VLT_CMP
Voltage Monitor Comparators Register
This register reads the state of the internal supply voltage monitors.
In the table above, note that reserved bits are grayed table cells and are not described in the bit description section below.
Reserved bits must always be written with a value of ‘0’. For additional information, refer to the
in the POR chapter.
1
LVD
This bit reads the state of the LVD comparator.
0
Vdd is above LVD trip point.
1
Vdd is below LVD trip point.
Individual Register Names and Addresses:
1,E4h
VLT_CMP : 1,E4h
7
6
5
4
3
2
1
0
Access : POR
R : 0
Bit Name
LVD
Bit
Name
Description
Summary of Contents for PSoC CY8CTMG20 Series
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