Cypress PSoC CY8CTMG20 Series, Technical Reference Manual

Page: 110 / 308

110 PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
Digital Clocks
14.1.2 Internal Low Speed Oscillator
The Internal Low Speed Oscillator (ILO) is available as a
general clock, but is also the clock source for the sleep and
watchdog timers. The ILO can be disabled in deep sleep
mode, or in other sleep modes when the External Crystal
Oscillator (ECO) is enabled.
The ILO is discussed in detail in the chapter Internal Low
Speed Oscillator (ILO) on page 67 .
Figure 14-1. Overview of PSoC Clock Sources
14.1.3 External Clock
In addition to the IMO clock source, an externally supplied
clock may be selected as the device master clock (see
Figure 14-1 ).
Pin P1[4] is the input pin for the external clock. If P1[4] is
selected as the external clock source, the drive mode of the
pin must be set to High Z (not High Z Analog).
An external clock with a frequency between 1 MHz and 24
MHz can be supplied. The reset state of the EXTCLKEN bit
is ‘0’. With this setting the device always boots up under the
control of the IMO. The system cannot be started from a
reset with the external clock.
When the EXTCLKEN bit is set, the external clock becomes
the source for the internal clock tree, SYSCLK, which drives
most PSoC device clocking functions. All external and inter-
nal signals, including the ILO or ECO low frequency clock,
are synchronized to this clock source.
14.1.3.1 Switch Operation
Switching between the IMO and the external clock is done in
firmware at any time and is transparent to the user.
When a switch is made from the IMO to the external clock,
turn off the IMO to save power. You do this by setting the
IMODIS bit immediately after the instruction that sets the
EXTCLKEN bit. When switching back from an external clock
to the IMO, clear the IMODIS bit and implement a firmware
delay. This gives the IMO sufficient startup time before the
EXTCLKEN bit is cleared.
Switch timing depends upon whether the CPU clock divider
is set for divide by 1, or divide by 2 or greater. In the case
where the CPU clock divider is set for divide by 2 or greater,
as shown in
Figure 14-2 , the setting of the EXTCLKEN bit
occurs shortly after the rising edge of SYSCLK. The
SYSCLK output is then disabled after the next falling edge of
SYSCLK, but before the next rising edge. This ensures a
glitch free transition and provides a full cycle of setup time
from SYSCLK to output disable. After the current clock
selection is disabled, the enable of the newly selected clock
is double synchronized to that clock. After synchronization,
on the subsequent negative edge, SYSCLK is enabled to
output the newly selected clock.
In the 12 MHz case, as shown in Figure 14-3 , the assertion
of IOW_ and thus the setting of the EXTCLKEN bit occurs
on the falling edge of SYSCLK. Since SYSCLK is already
low, the output is immediately disabled. Therefore, the setup
time from SYSCLK to disable is one-half SYSCLK.
SYSCLK
CPUCLK
SLEEP
Internal
Main
Oscillator
(IMO)
IMO Trim Register
CLK32K
EXTCLK
P1[4]
(EXTCLK Input)
IMO_TR[7:0]
OSC_CR2[2]
Clock Divider
OSC_CR0[2:0]
Sleep Clock Divider
OSC_CR0[4:3]
2
6
2
9
2
12
2
15
Slow IMO Option
CPU_SCR1[4:3]
1
2
4
8
16
32
128
256
ILO Trim Register
Internal Low
Speed
Oscillator
(ILO)
ILO_TR[7:0]
[+] Feedback