Cypress PSoC CY8CTMG20 Series, Technical Reference Manual

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248 PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
INT_MSK2
0,DEh
21.3.57 INT_MSK2
Interrupt Mask Register 2
This register enables the individual sources' ability to create pending interrupts.
When an interrupt is masked off, the mask bit is '0'. The interrupt continues to post in the interrupt controller. Clearing the
mask bit only prevents a posted interrupt from becoming a pending interrupt. In the table above, note that reserved bits are
grayed table cells and are not described in the bit description section below. Reserved bits must always be written with a
value of ‘0’. For additional information, refer to the
Register Definitions on page 48 in the Interrupt Controller chapter.
5 USB Wakeup 0 Mask USB Wakeup interrupt.
1 Unmask USB Wakeup interrup.
4 Endpoint8 0 Mask USB Endpoint8 interrupt.
1 Unmask USB Endpoint8 interrupt.
3 Endpoint7 0 Mask USB Endpoint7 interrupt.
1 Unmask USB Endpoint7 interrupt.
2 Endpoint6 0 Mask USB Endpoint6 interrupt.
1 Unmask USB Endpoint6 interrupt.
1 Endpoint5 0 Mask USB Endpoint5 interrupt.
1 Unmask USB Endpoint5 interrupt.
0 Endpoint4 0 Mask USB Endpoint4 interrupt.
1 Unmask USB Endpoint4 interrupt.
Individual Register Names and Addresses:
0,DEh
INT_MSK2 : 0,DEh
7 6 5 4 3 2 1 0
Access : POR RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0
Bit Name USB Wakeup Endpoint8 Endpoint7 Endpoint6 Endpoint5 Endpoint4
Bit Name Description
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