Cypress PSoC CY8CTMG20 Series, Technical Reference Manual

Page: 159 / 308

PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C 159
SPI
Figure 18-11 illustrates TX data loading in modes 0 and 1. A transfer in progress is defined to be from the falling edge of SS_
to the point at which the RX Buffer register is loaded with the received byte. This means that to send a byte in the next trans-
fer, it must be loaded into the TX Buffer register before the falling edge of SS_. This ensures a minimum setup time for the
first bit, since the leading edge of the first SCLK must latch in the received data. If SS_ is not toggled between each byte or is
forced low through the configuration register, the leading edge of SCLK is used to define the start of transfer. However, in this
case, the user must provide the required setup time (one-half clock minimum before the leading edge) with a knowledge of
system latencies and response times.
Figure 18-11. Mode 0 and 1 Transfer in Progress
Figure 18-12 illustrates TX data loading in modes 2 and 3. In this case, a transfer in progress is defined to be from the leading
edge of the first SCLK to the point at which the RX Buffer register is loaded with the received byte. Loading the shifter by the
leading edge of the clock has the effect of providing the required one-half clock setup time, as the data is latched into the
receiver on the trailing edge of the SCLK in these modes.
Figure 18-12. Mode 2 and 3 Transfer in Progress
SCLK (Mode 1)
SCLK (Mode 0)
SS Forced Low
SS Toggled on a Message Basis
SS Toggled on Each Byte
SS
Transfer in Progress
SCLK (Mode 1)
SCLK (Mode 0)
SS
Transfer in Progress Transfer in Progress
SCLK (Mode 1)
SCLK (Mode 0)
SS
Transfer in Progress Transfer in Progress
SCLK (Mode 3)
SCLK (Mode 2)
Transfer in Progress
(No Dependance on SS)
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