230
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
I2C_CP
0,CCh
21.3.42 I2C_CP
I
2
C Current Address Pointer Register
This register contains the current address value of the RAM data buffer and is read only.
In the table above, note that reserved bits are grayed table cells and are not described in the bit description section below.
Always write reserved bits with a value of ‘0’. For additional information, refer to the
Register Definitions on page 122
in the
I2C Slave chapter.
4:0
I2C Current Pointer[4:0]
This register is set at the same time and with the same value to which the I2C_BP register is set. After
each completed data byte of the current I2C transaction, the value of this register is incremented by
one. The value of this register always determines the location that read or write data comes from or is
written to.
This register is set to the value contained in the I2C_BP Register on every start condition detected in the
bus.
Individual Register Names and Addresses:
0,CCh
I2C_CP : 0,CCh
7
6
5
4
3
2
1
0
Access : POR
R : 00
Bit Name
I2C Current Pointer[4:0]
Bit
Name
Description
Summary of Contents for PSoC CY8CTMG20 Series
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Page 134: ...134 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C I2C Slave Feedback...
Page 142: ...142 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C System Resets Feedback...
Page 160: ...160 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C SPI Feedback...
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Page 302: ...302 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C Glossary Feedback...
