Cypress PSoC CY8CTMG20 Series, Technical Reference Manual

Page: 84 / 308

84 PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
Section C: TrueTouch System
TrueTouch Register Summary
The table below lists all the PSoC registers for the TrueTouch system in address order within their system resource configura-
tion. The bits that are grayed out are reserved bits. If these bits are written, always write them with a value of ‘0’.
Summary Table of the TrueTouch Registers
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access
TRUETOUCH MODULE REGISTERS (page 92 )
0,A0h CS_CR0 CSOUT[1:0]
CSD_
PRSCLK
CSD_CS_
CLK
CSD_
MODE
MODE[1:0] EN RW : 00
0,A1h CS_CR1 CHAIN CLKSEL[1:0] RLOCLK INV INSEL[2:0] RW : 00
0,A2h CS_CR2 IRANGE IDACDIR IDAC_EN CIN_EN PXD_EN CIP_EN RO_EN RW : 00
0,A3h CS_CR3 REFMUX REFMODE REF_EN LPFilt[1:0] LPF_EN[1:0] RW : 00
0,A4h CS_CNTL Data[7:0] RO : 00
0,A5h CS_CNTH Data[7:0] RO : 00
0,A6h CS_STAT INS COLS COHS PPS INM COLM COHM PPM # : 00
0,A7h CS_TIMER Timer Count Value[6:0] RW : 00
0,A8h CS_SLEW FastSlew[6:0] FS_EN RW : 00
0,A9h PRS_CR
CS_CLK_OU
T
CS_CLK_IN
V
PRS_12BIT PRS_EN PRESCALE_
BYP
PRESCALE_CLK_DIV[2:0] RW : 00
0,FDh IDAC_D DACDATA[7:0] RW : 00
IO ANALOG MULTIPLEXER REGISTERS (page 100 )
0,61h AMUX_CFG
PRX_
MODE
ICAPEN[1:0] INTCAP[1:0] RW : 00
1,D8h MUX_CR0 ENABLE[7:0] RW : 00
1,D9h MUX_CR1 ENABLE[7:0] RW : 00
1,DAh MUX_CR2 ENABLE[7:0] RW : 00
1,DBh MUX_CR3 ENABLE[7:0] RW : 00
1,DFh MUX_CR4 ENABLE[3:0] RW : 0
COMPARATOR REGISTERS (page 103 )
0,78h CMP_RDC CMP1D CMP0D CMP1L CMP0L # : 0
0,79h CMP_MUX INP1[1:0] INN1[1:0] INP0[1:0] INN0[1:0] RW : 00
0,7Ah CMP_CR0 CMP1EN CMP0EN RW : 0
0,7Bh CMP_CR1 CINT1 CPIN1 CRST1 CDS1 CINT0 CPIN0 CRST0 CDS0 RW : 00
0,7Ch CMP_LUT LUT1[3:0] LUT0[3:0] RW : 00
LEGEND
# Access is bit specific. Refer to the Register Reference chapter on page 187 for additional information.
R Read register or bit(s).
W Write register or bit(s).
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