216
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
CS_CNTH
0,A5h
21.3.28 CS_CNTH
TrueTouch Counter High Byte Register
This register contains the current count value for the high byte counter and is read only.
For additional information, refer to the
Register Definitions on page 92
in the TrueTouch Module chapter
.
7:0
Data[7:0]
On a read of this register, the current count is returned. It is only read when the counter is stopped.
Note
The counter must be stopped by the configured event. When the counter is disabled, the count
is reset to 00h.
Individual Register Names and Addresses:
0,A5h
CS_CNTH : 0,A5h
7
6
5
4
3
2
1
0
Access : POR
RO : 00
Bit Name
Data[7:0]
Bit
Name
Description
Summary of Contents for PSoC CY8CTMG20 Series
Page 4: ...4 Contents Overview Feedback...
Page 26: ...26 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C Section B PSoC Core Feedback...
Page 82: ...82 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C Sleep and Watchdog Feedback...
Page 134: ...134 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C I2C Slave Feedback...
Page 142: ...142 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C System Resets Feedback...
Page 160: ...160 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C SPI Feedback...
Page 182: ...182 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C Full Speed USB Feedback...
Page 302: ...302 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C Glossary Feedback...
