PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
211
CS_CR0
0,A0h
21.3.23 CS_CR0
TrueTouch Control Register 0
This register controls the operation of the TrueTouch counters.
Do not write bits [7:1] while the block is enabled. For additional information, refer to the
Register Definitions on page 92
TrueTouch Module chapter
.
7:6
CSOUT[1:0]
These bits select between a number of TrueTouch signals that can be driven to an output pin.
00b
IN.
01bCS_INT.
10bCOL.
11bCOH.
5
CSD_PRSCLK
This bit selects between IMO-P or the PRS output as a clock source to drive the main capacitor
switch.
0
Select IMO-P.
1
Select PRS Output.
4
CSD_CS_CLK
This bit selects between IMO or IMO-P for the TrueTouch counters to work. Depending on this bit
selection either IMO or IMO-P is sent as the source clock to the clock dividers which generate
CS_CLK as shown in
0
Select IMO.
1
Select IMO-P.
3
CSD_MODE
This bit enables the CSD mode. When this bit is enabled, the TIMER1 block works on IMO-P (pre-
scaled IMO) clock. This is also an enable for TrueTouch counters to toggle.
Note
:
Once the CSD_MODE bit is enabled, the IMO-P clock is a free running divider clock that
cannot be stopped and re-started. The IMO-P and the CPU clock are both derived from the
IMO clock but the phase relationship between them is nondeterministic.
0
Disable CSD mode. Programmable Timer1 works on either CPUCLK/CLK32, (depends on
CLKSEL bit selection in PT1_CFG (0, B3h) register).
1
Enable CSD mode. When this bit is set to 1, Programmable Timer1 works on IMO-P.
2:1
MODE[1:0]
TrueTouch Counter Mode.
00b
Event Mode. Start in enable, stop on interrupt event.
01b
Pulse Width Mode. Start on positive edge of next input. Stop on negative edge of input.
10b
Period Mode. Start on positive edge of input. Stop on next positive edge of input.
11b
Start in enable, continuous operation until disable.
0
EN
0
Counting is stopped and all counter values are reset to zero.
1
Counters are enabled for counting.
Individual Register Names and Addresses:
0,A0h
CS_CR0 : 0,A0h
7
6
5
4
3
2
1
0
Access : POR
RW : 0
RW : 0
RW : 0
RW : 0
RW : 0
RW : 0
Bit Name
CSOUT[1:0]
CSD_
PRSCLK
CSD_CS_
CLK
CSD_
MODE
MODE[1:0]
EN
Bit
Name
Description
Summary of Contents for PSoC CY8CTMG20 Series
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