Cypress PSoC CY8CTMG20 Series, Technical Reference Manual

Page: 51 / 308

PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C 51
Interrupt Controller
5.3.4 INT_MSK0 Register
The Interrupt Mask Register (INT_MSK0) enables the indi-
vidual interrupt sources’ ability to create pending interrupts.
If cleared, each bit in an INT_MSK0 register prevents a
posted interrupt from becoming a pending interrupt (input to
the Priority Encoder). However, an interrupt can still post
even if its mask bit is zero. All INT_MSK0 bits are indepen-
dent of all other INT_MSK0 bits.
If an INT_MSK0 bit is set, the interrupt source associated
with that mask bit may generate an interrupt that becomes a
pending interrupt. For example, if INT_MSK0[4] is set and at
least one GPIO pin is configured to generate an interrupt,
the interrupt controller allows a GPIO interrupt request to
post and become a pending interrupt to which the M8C
responds. If a higher priority interrupt is generated before
the M8C responds to the GPIO interrupt, the higher priority
interrupt is responded to before the GPIO interrupt.
Each interrupt source may require configuration at a block
level. Refer to the corresponding chapter for each interrupt
for any additional configuration information.
Bit 7: I2C. This bit allows I2C interrupts to be enabled or
masked.
Bit 6: Sleep. This bit allows sleep interrupts to be enabled
or masked.
Bit 5: SPI. This bit allows SPI interrupts to be enabled or
masked.
Bit 4: GPIO. This bit allows GPIO interrupts to be enabled
or masked.
Bit 3: Timer0. This bit allows Timer0 interrupts to be
enabled or masked.
Bit 2: TrueTouch. This bit allows TrueTouch interrupts to
be enabled or masked.
Bit 1: Analog. This bit allows analog interrupts to be
enabled or masked.
Bit 0: V Monitor. This bit allows voltage monitor interrupts
to be enabled or masked.
For additional information, refer to the INT_MSK0 register
on page 250 .
5.3.5 INT_MSK1 Register
This register enables the individual sources' ability to create
pending interrupts.
When an interrupt is masked off, the mask bit is '0'. The
interrupt continues to post in the interrupt controller. Clear-
ing the mask bit only prevents a posted interrupt from
becoming a pending interrupt.
Bit 7: Endpoint3. ’0’ is mask USB Endpoint3 interrupt. ‘1’
is unmask USB Endpoint3 interrupt.
Bit 6: Endpoint2. ’0’ is mask USB Endpoint2 interrupt. ‘1’
is unmask USB Endpoint2 interrupt.
Bit 5: Endpoint1. ’0’ is mask USB Endpoint1 interrupt. ‘1’
is unmask USB Endpoint1 interrupt.
Bit 4: Endpoint0. ’0’ is mask USB Endpoint0 interrupt. ‘1’
is unmask USB Endpoint0 interrupt.
Bit 3: USB SOF. ’0’ is mask USB SOF interrupt. ‘1’ is
unmask USB SOF interrupt.
Bit 2: USB Bus Reset(K). ’0’ is mask USB Bus Reset
interrupt. ‘1’ is unmask USB Bus Reset interrupt.
Bit 1: Timer2. ’0’ is mask Timer2 interrupt. ‘1’ is unmask
Timer2 interrupt.
Bit 0: Timer1. ’0’ is mask Timer1 interrupt. ‘1’ is unmask
Timer1 interrupt.
For additional information, refer to the INT_MSK1 register
on page 249 .
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access
0,E0h INT_MSK0 I2C Sleep SPI GPIO Timer0 TrueTouch Analog V Monitor RW : 00
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access
0,DFh INT_MSK1 Endpoint3 Endpoint2 Endpoint1 Endpoint0 USB SOF USB Bus Reset Timer2 Timer1 RW : 00
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