Cypress PSoC CY8CTMG20 Series, Technical Reference Manual

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250 PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
INT_MSK0
0,E0h
21.3.59 INT_MSK0
Interrupt Mask Register 0
This register enables the individual sources’ ability to create pending interrupts.
When an interrupt is masked off, the mask bit is ‘0’. The interrupt continues to post in the interrupt controller. Clearing the
mask bit only prevents a posted interrupt from becoming a pending interrupt. For additional information, refer to the
Register
Definitions on page 48 in the Interrupt Controller chapter.
7 I2C 0 Mask I2C interrupt.
1 Unmask I2C interrupt.
6 Sleep 0 Mask Sleep interrupt.
1 Unmask Sleep interrupt.
5 SPI 0 Mask SPI interrupt.
1 Unmask SPI interrupt.
4 GPIO 0 Mask GPIO interrupt.
1 Unmask GPIO interrupt.
3 Timer0 0 Mask Timer0 interrupt.
1 Unmask Timer0 interrupt.
2 TrueTouch 0 Mask TrueTouch interrupt.
1 Unmask TrueTouch interrupt.
1 Analog 0 Mask Analog interrupt.
1 Unmask Analog interrupt.
0 V Monitor 0 Mask Voltage Monitor interrupt.
1 Unmask Voltage Monitor interrupt.
Individual Register Names and Addresses:
0,E0h
INT_MSK0 : 0,E0h
7 6 5 4 3 2 1 0
Access : POR RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0
Bit Name I2C Sleep SPI GPIO Timer0 TrueTouch Analog V Monitor
Bit Name Description
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