Cypress PSoC CY8CTMG20 Series, Technical Reference Manual

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PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C 45
5. Interrupt Controller
This chapter presents the Interrupt Controller and its associated registers. The interrupt controller provides a mechanism for a
hardware resource in PSoC devices to change program execution to a new address without regard to the current task being
performed by the code being executed. For a quick reference of all PSoC registers in address order, refer to the
Register
Reference chapter on page 187 .
5.1 Architectural Description
A block diagram of the Interrupt Controller is shown in Figure 5-1 , illustrating the concepts of posted interrupts and pending
interrupts .
Figure 5-1. Interrupt Controller Block Diagram
This is the sequence of events that occur during interrupt
processing.
1. An interrupt becomes active, either because (a) the
interrupt condition occurs (for example, a timer expires),
(b) a previously posted interrupt is enabled through an
update of an interrupt
mask register, or (c) an interrupt is
pending and GIE is set from ‘0’ to ‘1’ in the CPU Flag
register.
2. The current executing instruction finishes.
3. The internal interrupt service routine (ISR) executes, tak-
ing 13 cycles. During this time, the following actions
occur:
■
The PCH, PCL, and Flag register (CPU_F) are pushed
onto the stack (in that order).
■
The CPU_F register clears. Since this clears the GIE bit
to ‘0’, additional interrupts are temporarily disabled.
■
The PCH (PC[15:8]) is cleared to zero.
■
The interrupt vector is read from the interrupt controller
and its value is placed into PCL (PC[7:0]). This sets the
program counter to point to the appropriate address in
the interrupt table (for example, 0014h for the GPIO
interrupt).
M8C Core
Interrupt
Source
(Timer,
GPIO, etc.)
Interrupt Taken
or
Posted
Interrupt
Pending
Interrupt
GIE
Interrupt Vector
Mask Bit Setting
D
R
Q 1
Priority
Encoder
Interrupt
Request
...
INT_MSKx
INT_CLRx:n Write
CPU_F[0]
...
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