PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
199
EP0_CNT
0,37h
21.3.12 EP0_CNT
Endpoint 0 Count Register
The Endpoint 0 Count register (EP0_CNT) configures endpoint 0.
In the table above, note that reserved bits are grayed table cells and are not described in the bit description section below.
Reserved bits must always be written with a value of ‘0’. For additional information, refer to the
in the Full-Speed USB chapter.
7
Data Toggle
This bit selects the data packet's toggle state.
6
Data Valid
This bit indicates whether there were errors in OUT or setup transactions.
3:0
Byte Count[3:0]
These bits indicate the number of data bytes in a transaction.
Individual Register Names and Addresses:
0,37h
EP0_CNT : 0,37h
7
6
5
4
3
2
1
0
Access : POR
RW : 0
RC : 0
RW : 0
Bit Name
Data Toggle
Data Valid
Byte Count[3:0]
Bit
Name
Description
Summary of Contents for PSoC CY8CTMG20 Series
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Page 26: ...26 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C Section B PSoC Core Feedback...
Page 82: ...82 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C Sleep and Watchdog Feedback...
Page 134: ...134 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C I2C Slave Feedback...
Page 142: ...142 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C System Resets Feedback...
Page 160: ...160 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C SPI Feedback...
Page 182: ...182 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C Full Speed USB Feedback...
Page 302: ...302 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C Glossary Feedback...
