Cypress PSoC CY8CTMG20 Series, Technical Reference Manual

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258 PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
CPU_SCR0
x,FFh
21.3.66 CPU_SCR0
System Status and Control Register 0
This register is used to convey the status and control of events for various functions of a PSoC device.
In the table above, note that reserved bits are grayed table cells and are not described in the bit description section below.
Reserved bits must always be written with a value of ‘0’. For additional information, refer to the
Register Definitions on
page 137 in the System Resets chapter.
7 GIES Global Interrupt Enable Status. It is recommended that the user read the Global Interrupt Enable Flag
bit from the
CPU_F register on page 254 . This bit is read only for GIES. Its use is discouraged, as the
Flag register is now readable at address x,F7h (read only).
5 WDRS Watchdog Reset Status. This bit may not be set by user code; however, it may be cleared by writing
a ’0’.
0
No watchdog reset has occurred.
1 Watchdog reset has occurred.
4 PORS Power On Reset Status. This bit may not be set by user code; however, it may be cleared by writing a
’0’.
0
Power on reset has not occurred and watchdog timer is enabled.
1 Is set after external reset or power on reset.
3 Sleep Set by the user to enable the CPU sleep state. CPU remains in Sleep mode until any interrupt is
pending.
0
Normal operation.
1 Sleep.
0 STOP 0 M8C is free to execute code.
1 M8C is halted and is only cleared by POR, XRES, or WDR.
Individual Register Names and Addresses:
x,FFh
CPU_SCR0 : x,FFh
7 6 5 4 3 2 1 0
Access : POR R : 0 RC : 0 RC : 1 RW : 0 RW : 0
Bit Name GIES WDRS PORS Sleep STOP
Bit Name Description
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