Cypress PSoC CY8CTMG20 Series, Technical Reference Manual

Page: 246 / 308

246 PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
INT_CLR2
0,DCh
21.3.56 INT_CLR2
Interrupt Clear Register 2
This register is used to enable the individual interrupt sources' ability to clear posted interrupts.
When bits in this register are read, a '1' is returned for every bit position that has a corresponding posted interrupt. When bits
in this register are written with a '0' and ENSWINT is not set, posted interrupts are cleared at the corresponding bit positions.
If there is no posted interrupt, there is no effect. In the table above, note that reserved bits are grayed table cells and are not
described in the bit description section below. Reserved bits must always be written with a value of ‘0’. When bits in this reg-
ister are written with a '1' and ENSWINT is set, an interrupt is posted in the interrupt controller. For additional information,
refer to the
Register Definitions on page 48 in the Interrupt Controller chapter.
5 USB_WAKE Read 0 No posted interrupt for USB Wake.
Read 1 Posted interrupt present for USB Wake.
Write 0 AND ENSWINT = 0 Clear posted interrupt if it exists.
Write 1 AND ENSWINT = 0 No effect.
Write 0 AND ENSWINT = 1 No effect.
Write 1 AND ENSWINT = 1 Post an interrupt for USB Wake.
4 Endpoint8 Read 0 No posted interrupt for USB Endpoint8.
Read 1 Posted interrupt present for USB Endpoint8.
Write 0 AND ENSWINT = 0 Clear posted interrupt if it exists.
Write 1 AND ENSWINT = 0 No effect.
Write 0 AND ENSWINT = 1 No effect.
Write 1 AND ENSWINT = 1 Post an interrupt for USB Endpoint8.
(continued on next page)
Individual Register Names and Addresses:
0,DCh
INT_CLR2 : 0,DCh
7 6 5 4 3 2 1 0
Access : RW:00 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0
Bit Name USB_WAKE Endpoint8 Endpoint7 Endpoint6 Endpoint5 Endpoint4
Bit Name Description
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