PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
225
PT2_CFG
0,B6h
21.3.37 PT2_CFG
Programmable Timer 2 Configuration Register
This register configures the programmable timer 2.
In the table above, note that reserved bits are grayed table cells and are not described in the bit description section below.
Reserved bits must always be written with a value of ‘0’. For additional information, refer to the
in the Programmable Timer chapter
.
2
CLKSEL
This bit determines if the timer runs on the 32 kHz clock or CPU clock. If the bit is set to 1'b1, the timer
runs on the CPU clock, otherwise, the timer runs on the 32 kHz clock.
1
One Shot
0
Continuous count mode. Timer reloads the count value from the data registers upon each
terminal count, and continues counting.
1
One-shot mode. Timer goes through one complete count period and then stops. Upon com-
pletion, the START bit in this register is cleared.
0
START
0
Timer held in reset.
1
Timer counts down from a full count determined from its data registers (PT_DATA1,
PT_DATA0). When complete, it either stops or reloads and continues, based on the One
Shot bit in this register.
Individual Register Names and Addresses:
0,B6h
PT2_CFG : 0,B6h
7
6
5
4
3
2
1
0
Access : POR
RW : 0
RW : 0
RW : 0
Bit Name
CLKSEL
One Shot
START
Bit
Name
Description
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