PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
197
USBIO_CR1
0,35h
21.3.10 USBIO_CR1
USB I/O Control Register 1
This register is a USBIO manual control register 1.
For additional information, refer to the
Register Definitions on page 171
in the Full-Speed USB chapter.
7
IOMode
This bit allows the configuration of D+ and D- pins.
6
Drive Mode
This bit configures D+ and D- pins for either CMOS drive or open drain drive.
5
DPI
This bit drives the D+ pin if IOMode=1.
4
DMI
This pin drives the D- pin if IOMode=1.
3
PS2PUEN
This bit controls the connection of the two internal 5 k
Ω
pull up resistors to the D+ and D- pins.
2
USBPUEN
This bit controls the connection of the internal 1.5 k
Ω
pull up resistor on the D+ pin.
1
DPO
This read only bit provides the D+ pin status.
0
DMO
This read only bit provides the D- pin status.
Individual Register Names and Addresses:
0,35h
USBIO_CR1 : 0,35h
7
6
5
4
3
2
1
0
Access : POR
RW : 0
RW : 0
RW : 0
RW : 0
RW : 0
RW : 0
R :1
R : 1
Bit Name
IOMode
Drive Mode
DPI
DMI
PS2PUEN
USBPUEN
DPO
DMO
Bit
Name
Description
Summary of Contents for PSoC CY8CTMG20 Series
Page 4: ...4 Contents Overview Feedback...
Page 26: ...26 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C Section B PSoC Core Feedback...
Page 82: ...82 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C Sleep and Watchdog Feedback...
Page 134: ...134 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C I2C Slave Feedback...
Page 142: ...142 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C System Resets Feedback...
Page 160: ...160 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C SPI Feedback...
Page 182: ...182 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C Full Speed USB Feedback...
Page 302: ...302 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C Glossary Feedback...
