Section 11 Local Bus State Controller (LBSC)
Rev. 1.00 Oct. 01, 2007 Page 344 of 1956
REJ09B0256-0100
Bit Bit
Name
Initial
Value
R/W Description
9, 8
SZ
11
R/W
*
Bus
Width
Specify the bus width. In CS0BCR, the external pins
(MD3 and MD4) are sampled at a power-on reset. Set
to 11 for the MPX interface, and set to 10 or 11 for the
byte control SRAM interface.
00: Reserved
01: 8 bits
10: 16 bits
11: 32 bits
Note:
*
Bits SZ in CS0BCR are read-only. The SZ bits
in CS0BCR are set to 11 when area 0 is set to
MPX interface by the MD3 and MD4 pins.
7 RDSPL
0 R/W
RD
Hold Cycle
Specify the number of cycles to be inserted into the
RD
assertion period to ensure the data hold time to the
read data sample timing. When set this bit to 1, specify
the number of
RD
negation-
CSn
negation delay cycle to
be 1 or more by setting the RDH bit in CSnWCR. And
RD
negation-
CSn
negation delay cycle is reduced 1
cycle to set this bit to 1 (Available only when the SRAM
interface or byte control SRAM interface).
0: No hold cycle inserted
1: 1 hold cycle inserted
6 to 4
BW
111
R/W
Burst Pitch
When the burst ROM interface is used, these bits
specify the number of wait cycles to be inserted after
the second data access in a burst transfer.
000: No idle cycle inserted,
RDY
signal disabled
001: 1 idle cycle inserted,
RDY
signal enabled
010: 2 idle cycles inserted,
RDY
signal enabled
011: 3 idle cycles inserted,
RDY
signal enabled
100: 4 idle cycles inserted,
RDY
signal enabled
101: 5 idle cycles inserted,
RDY
signal enabled
110: 6 idle cycles inserted,
RDY
signal enabled
111: 7 idle cycles inserted,
RDY
signal enabled
Summary of Contents for SH7763
Page 2: ...Rev 1 00 Oct 01 2007 Page ii of lxvi ...
Page 122: ...Section 2 Programming Model Rev 1 00 Oct 01 2007 Page 56 of 1956 REJ09B0256 0100 ...
Page 144: ...Section 3 Instruction Set Rev 1 00 Oct 01 2007 Page 78 of 1956 REJ09B0256 0100 ...
Page 170: ...Section 4 Pipelining Rev 1 00 Oct 01 2007 Page 104 of 1956 REJ09B0256 0100 ...
Page 282: ...Section 7 Caches Rev 1 00 Oct 01 2007 Page 216 of 1956 REJ09B0256 0100 ...
Page 378: ...Section 9 Interrupt Controller INTC Rev 1 00 Oct 01 2007 Page 312 of 1956 REJ09B0256 0100 ...
Page 514: ...Section 12 DDR SDRAM Interface DDRIF Rev 1 00 Oct 01 2007 Page 448 of 1956 REJ09B0256 0100 ...
Page 630: ...Section 13 PCI Controller PCIC Rev 1 00 Oct 01 2007 Page 564 of 1956 REJ09B0256 0100 ...
Page 710: ...Section 16 Clock Pulse Generator CPG Rev 1 00 Oct 01 2007 Page 644 of 1956 REJ09B0256 0100 ...
Page 732: ...Section 17 Watchdog Timer and Reset WDT Rev 1 00 Oct 01 2007 Page 666 of 1956 REJ09B0256 0100 ...
Page 752: ...Section 18 Power Down Mode Rev 1 00 Oct 01 2007 Page 686 of 1956 REJ09B0256 0100 ...
Page 772: ...Section 19 Timer Unit TMU Rev 1 00 Oct 01 2007 Page 706 of 1956 REJ09B0256 0100 ...
Page 824: ...Section 21 Compare Match Timer CMT Rev 1 00 Oct 01 2007 Page 758 of 1956 REJ09B0256 0100 ...
Page 1124: ...Section 26 I 2 C Bus Interface IIC Rev 1 00 Oct 01 2007 Page 1058 of 1956 REJ09B0256 0100 ...
Page 1350: ...Section 30 SIM Card Module SIM Rev 1 00 Oct 01 2007 Page 1284 of 1956 REJ09B0256 0100 ...
Page 1484: ...Section 33 Audio Codec Interface HAC Rev 1 00 Oct 01 2007 Page 1418 of 1956 REJ09B0256 0100 ...
Page 1560: ...Section 35 USB Host Controller USBH Rev 1 00 Oct 01 2007 Page 1494 of 1956 REJ09B0256 0100 ...
Page 1720: ...Section 37 LCD Controller LCDC Rev 1 00 Oct 01 2007 Page 1654 of 1956 REJ09B0256 0100 ...
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Page 2026: ...SH7763 Hardware Manual ...